When placed near the USB connectors, the TPD6E004 ESD solution offers little or no signal distortion during
normal operation due to low I/O capacitance and ultra-low leakage current
specifications. The TPD6E004 is designed to protect the core
circuitry and allow the system to function properly in the event of an ESD strike.
For proper operation, the Layout Guidelines and following design guidelines must be
followed:
- Place the TPD6E004 solution close to the connectors. This allows the
TPD6E004 to take away the energy associated with ESD
strike before it reaches the internal circuitry of the system board.
- Place a 0.1-μF capacitor very
close to the VCC pin. This limits any momentary voltage surge at
the I/O pin during the ESD strike event.
- Ensure that there is enough
metallization for the VCC and GND loop. During normal operation,
the TPD6E004 consumes only μA of leakage current, but
during an ESD event, VCC and GND may see 15-A to 30-A of current,
depending on the ESD level. A sufficient current path enables the safe
discharge of all the energy associated with the ESD strike.
- Leave any unused I/O pins
floating. In this example of protecting two Micro-B USB ports, none of the
I/O pins are left unused.
- The VCC pin can be
connected in two different ways:
- If the VCC
pin is connected to the system power supply, then the TPD6E004 works as a transient suppressor for any
signal swing above VCC + VF. TI recommends a
0.1-μF capacitor on the device VCC pin for ESD
bypass.
- If the VCC
pin is not connected to the system power supply, then the TPD6E004 can tolerate a higher signal swing in the
range of up to 5.8 V.
Note: A 0.1-μF capacitor
is still recommended at the VCC pin for ESD
bypass.