The TPD7S019 device is an integrated electrostatic discharge (ESD) circuit protection solution for VGA and DVI-I connectors. It integrates transient voltage suppression (TVS) protection diodes for VIDEO, DDC and SYNC signals and meets the IEC61000-4-2 standard for ±8-kV contact ESD protection. The TVS diodes only add low capacitances to help signals run at high-speed. It also provides level-shifting for the DDC signals saving external level-shifters. Two noninverting drivers on HSYNC and VSYNC convert TTL input levels to CMOS output levels and each buffer has a series termination resistor connected to the SYNC_OUT pin, eliminating the external termination resistors. Three supply lines control the power rails of the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage video controller ICs in mixed supply-voltage environments. The TPD7S019 comes with two package options. The 16-pin RSV is compact and space-saving. The 16-pin DBQ package and pinout are optimized for easy board layout.
This ESD protection product is a good solution to protect the VGA and DVI-I ports for desktop and laptop PCs, set top boxes, TVs and monitors.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPD7S019 | SSOP (16) | 4.90 mm × 3.90 mm |
UQFN (16) | 2.60 mm × 1.80 mm |
Changes from D Revision (April 2016) to E Revision
Changes from C Revision (November 2015) to D Revision
Changes from B Revision (December 2012) to C Revision
Changes from * Revision (August 2010) to A Revision
Changes from A Revision (March 2012) to B Revision
PIN | TYPE | DESCRIPTION | ||
---|---|---|---|---|
NAME | DBQ | RSV | ||
BYP | 8 | 6 | Power | Bypass pin. Using a 0.2-µF bypass capacitor increases the ESD robustness of the system |
DDC_IN1 | 10 | 8 | I | DDC signal input. Connects to the VGA controller side of one of the sync lines |
DDC_IN2 | 11 | 9 | ||
DDC_OUT1 | 9 | 7 | O | DDC signal output. Connects to the video connector side of one of the sync lines |
DDC_OUT2 | 12 | 10 | ||
GND | 6 | 4 | — | Ground |
SYNC_IN1 | 13 | 11 | I | Sync signal buffer input. Connects to the VGA controller side of one of the sync lines |
SYNC_IN2 | 15 | 13 | ||
SYNC_OUT1 | 14 | 12 | O | Sync signal buffer output. Connects to the video connector side of one of the sync lines |
SYNC_OUT2 | 16 | 14 | ||
VCC_DDC | 7 | 5 | Power | Isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates |
VCC_SYNC | 1 | 15 | Power | Isolated supply input for the SYNC_1 and SYNC_2 level-shifters and their associated ESD protection circuits |
VCC_VIDEO | 2 | 16 | Power | Supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection circuits |
VIDEO1 | 3 | 1 | ESD | High-speed ESD clamp input |
VIDEO2 | 4 | 2 | ||
VIDEO3 | 5 | 3 |
MIN | MAX | UNIT | |||||
---|---|---|---|---|---|---|---|
Supply voltage | VCC_VIDEO | –0.5 | 6 | V | |||
VCC_DDC | –0.5 | 6 | |||||
VCC_SYNC | –0.5 | 6 | |||||
IO voltage | VIO(VIDEO) | VIDEOx pins | –0.5 | VCC_VIDEO | V | ||
Input voltage | VI(SYNC) | SYNC pins | –0.5 | VCC_SYNC | V | ||
VI(DDC) | DDC_INx pins | –0.5 | 6 | V | |||
Output voltage | VO(DDC) | DDC_INx pins | –0.5 | 6 | V | ||
Input clamp current | IIK | SYNC_INx, DDC_INx, VIDEOx | VI < 0 | –50 | mA | ||
Output clamp current | IOK | SYNC_OUTx, DDC_OUTx | VO < 0 | –50 | mA | ||
Continuous output current | IO | SYNC_OUTx | –24 | 24 | mA | ||
DDC_INx to DDC_OUTx | –5 | 5 | mA | ||||
Continuous current through supply pins | VCC_VIDEO, VCC_SYNC, VCC_DDC | –50 | 50 | mA | |||
Storage temperature | Tstg | –55 | 125 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
TPD7S019 in RSV Package | |||||
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins except 1, 2, 3, 4, 7, 10, 12, and 14 | ±2000 | V |
Pins 1, 2, 3, 7, 10, 12, and 14 | ±15000 | ||||
Pin 4 | ±2000 | ||||
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | ||||
IEC 61000-4-2 contact discharge | Pins 1, 2, 3, 7, 10, 12, and 14 | ±8000 | |||
TPD7S019 in DBQ Package | |||||
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins except 3, 4, 5, 6, 9, 12, 14, and 16 | ±2000 | V |
Pins 3, 4, 5, 9, 12, 14, and 16 | ±15000 | ||||
Pin 6 | ±2000 | ||||
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | ||||
IEC 61000-4-2 contact discharge | Pins 3, 4, 5, 9, 12, 14, and 16 | ±8000 |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
Supply voltage | VCC_VIDEO | 0 | 5.5 | V | ||
VCC_DDC | 0 | 5.5 | ||||
VCC_SYNC | 0 | 5.5 | ||||
IO voltage | VIO(VIDEO) | VIDEOx pins | 0 | VCC_VIDEO | V | |
Input voltage | VI(SYNC) | SYNC pins | 0 | VCC_SYNC | V | |
VI(DDC) | DDC_INx pins | 0 | 5.5 | V | ||
Output voltage | VO(DDC) | DDC_INx Pins | 0 | 5.5 | V | |
Operating temperature | TA | –40 | 85 | °C |
THERMAL METRIC(1) | TPD7S019 | UNIT | ||
---|---|---|---|---|
DBQ (SSOP) | RSV (UQFN) | |||
16 PINS | 16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 115.8 | 124.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 67 | 52.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 58.3 | 53.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 19.9 | 1.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 57.9 | 53.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
ICC_VIDEO | VCC_VIDEO supply current | VCC_VIDEO = 5 V, VIDEO inputs at VCC_VIDEO or GND | 1 | 10 | µA | |||
ICC_DDC | VCC_DDC supply current | VCC_DDC = 5 V | 1 | 10 | µA | |||
ICC_SYNC | VCC_SYNC supply current | VCC_SYNC = 5 V | SYNC inputs at GND or VCC_SYNC, SYNC outputs unloaded |
1 | 50 | µA | ||
SYNC inputs at 3 V; SYNC outputs unloaded |
2 | mA | ||||||
IIO_VIDEO | VIDEO input and output pins | VIO_VIDEO = 3 V | 0.01 | 1 | µA | |||
IOFF | DDC pin power down leakage current | VCC_DDC ≤ 0.4 V, VDDC_OUT = 5 V | 0.01 | 1 | µA | |||
VD | Diode forward voltage for lower clamp of VIDEO, DDC, SYNC output pins | ID = 8 mA, lower clamp diode | –0.6 | –0.8 | –0.95 | V | ||
RDYN_VIDEO | Dynamic resistance (VIDEO pins) | I = 1 A | 1 | Ω | ||||
VIH | High-level SYNC logic input voltage | VCC_SYNC = 5 V | 2 | V | ||||
VIL | Low-level SYNC logic input voltage | VCC_SYNC = 5 V | 0.6 | V | ||||
VOH | High-level SYNC logic output voltage | IOH = 0 mA, VCC_SYNC = 5 V | 4.85 | V | ||||
VOH | High-level SYNC logic output voltage | IOH = –24 mA, VCC_SYNC = 5 V | 2 | V | ||||
VOL | Low-level SYNC logic output voltage | IOL = 0 mA, VCC_SYNC = 5 V | 0.15 | V | ||||
VOL | Low-level SYNC logic output voltage | IOL = 24 mA, VCC_SYNC = 5 V | 0.8 | V | ||||
RT | SYNC driver output resistance | VCC_SYNC = 5 V, SYNC inputs at GND or 3 V | 15 | Ω | ||||
CIO_VIDEO | IO capacitance of VIDEO pins | VIO = 2.5 V, test frequency is 1 MHz | 2.5 | 4 | pF | |||
tPLH | SYNC driver L => H propagation delay | CL = 50 pF; VCC = 5 V, input tR and tF ≤ 5ns | 12 | ns | ||||
tPHL | SYNC driver H => L propagation delay | CL = 50 pF; VCC = 5 V, input tR and tF ≤ 5ns | 12 | ns | ||||
tR, tF | SYNC driver output rise & fall times | CL = 50 pF; VCC = 5 V, input tR and tF ≤ 5ns | 4 | ns | ||||
VBR | VIDEO ESD diode break-down voltage | IIO = 1 mA | 9 | V |
VCC_DDC = 0 V |
The TPD7S019 is an integrated protection solution for VGA or DVI-I ports by providing high-speed ESD protection, level-shifting and signal buffering. The TVS protection diodes for VIDEO signals, DDC signals and SYNC signals provide robust ESD clamping that meets the IEC61000-4-2 standard for ±8-kV contact stress. The signals run at high speed is minimally affected by the low capacitance added to each signal line. The integrated level-shifters for the DDC signals help save external ICs. Two buffers on the HSYNC and VSYNC signals convert TTL input level to CMOS output level, and it saves external components by integrating series termination resistors connected to the SYNC_OUT pin. The TPD7S019 takes in three signal rails to make the signals compatible with different voltages on VIDEO, DDC and SYNC. The two package options provide the latitude to choose between either small board area or easier layout and better signal integrity.
The end applications of this device include desktop and laptop PCs, set top boxes, TVs, and monitors.
The TPD7S019 is an integrated protection solution for VGA and DVI-I ports. It has the low capacitance ESD TVS diodes for the VIDEO signals to ensure high speed data transmission. Level-shifting on the DDC lines translate signals on the cable to the level can be processed by downstream ICs. Buffers on the SYNC lines condition the signal levels and quality. The integrated termination resistors help reduce external devices. The TPD7S019 exceeds IEC61000-4-2 (Level 4) ESD standard of ±8-kV contact discharge, making the system robust against system level ESD. The two package options provide the freedom to choose between a compact package or a flow through package.
DDC level translators and SYNC signal buffers are active and the ESD cells on all the lines are untriggered when the recommended operating conditions are met. The bidirectional voltage-level translators provide noninverting level-shifting from the system side to the connector side. Each connector side pin has an ESD clamp that triggers when voltages are above VBR or below the lower diode's Vf. During ESD events, voltages as high as ±8-kV (contact ESD) can be directed to ground through the internal diode network. Once the voltages on the protected line fall below these trigger levels (usually within 10s of nano-seconds), these pins revert to a non-conductive state.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
When a system contains a human interface connector, it becomes vulnerable to large system-level ESD strikes that standard ICs cannot survive. The TPD7S019 provides IEC61000-4-2 Level 4 Contact ESD rating to the VGA or DVI-I port. The integrated voltage level-shifting, buffering and termination reduce the board space needed to implement the control lines functions.
In this application, the TPD7S019 is used to protect the VGA port. Table 1 lists the system parameters.
DESIGN PARAMETER | VALUE |
---|---|
Pull-up resistors on DDC lines | 1.5 kΩ to 2 kΩ |
Termination resistors on VIDEO lines | 50 Ω to 75 Ω |
VIDEO signals data rate | 24 MHz to 388 MHz |
Required IEC 61000-4-2 ESD Protection | ±8-kV Contact |
To begin the design process, some parameters must be decided upon; the designer must make sure:
For this application, the DDC signals switch between 0 V and 5 V (with resistor pulling it up to 5-V power supply). The VIDEO and SYNC signal levels are between 0 V and VCC_VIDEO / VCC_SYNC. All signals are not exceeding the recommended values and the ESD cells on these pins stay untriggered.
Depending on the resolution and the refresh rate of the display, the VIDEO (RGB) signals' bandwidth can be from 24 MHz to 388 MHz. The line capacitances from the ESD cells are 2.5 pF typical which is only takes up a small portion of the total capacitance budget for the maximum frequency in this range.
±8-kV Contact ESD provided by the TPD7S019 meets the ESD design goal of ±8 kV contact.
Put 1.5-kΩ to 2-kΩ pullup resistor on the DDC lines to be compliant with the I2C standard. Termination resistors on VIDEO lines are 50 Ω to 75 Ω to match the impedance on board trace.
The TPD7S019 has three power supply pins: VCC_DDC, VCC_SYNC and VCC_VIDEO. Depending on the system, the recommended voltage level of these three power supplies can be as high as 5.5 V.