SLIS117C August   2007  – May 2022 TPIC1021A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Test Circuit
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Local Interconnect Network (LIN) Bus
        1. 10.3.1.1 Transmitter Characteristics
        2. 10.3.1.2 Receiver Characteristics
      2. 10.3.2 Transmit Input (TXD)
        1. 10.3.2.1 TXD Dominant State Time-Out
      3. 10.3.3 Receive Output (RXD)
        1. 10.3.3.1 RXD Wake-up Request
      4. 10.3.4 Supply Voltage (VSUP)
      5. 10.3.5 Ground (GND)
      6. 10.3.6 Enable Input (EN)
      7. 10.3.7 NWake Input (NWake)
      8. 10.3.8 Inhibit Output (INH)
    4. 10.4 Device Functional Modes
      1. 10.4.1 Operating States
        1. 10.4.1.1 Normal Mode
        2. 10.4.1.2 Sleep Mode
          1. 10.4.1.2.1 Wake-Up Events
        3. 10.4.1.3 Standby Mode
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
    3. 11.3 Power Supply Recommendations
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Electrical Characteristics

VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
SUPPLY
Operational supply voltage(2) Device is operational beyond the LIN 2.0 defined nominal supply line voltage range of 7 V < VSUP < 18 V 7 14 27 V
Nominal supply line voltage Normal and standby modes 7 14 18
Sleep mode 7 12 18
VSUP undervoltage threshold 4.5 6.2
ICC Supply current Normal mode, EN = High, Bus dominant (total bus load where RLIN ≥ 500 Ω and CLIN ≤ 10 nF (see Figure 9-1)(3), INH = VSUP, NWake = VSUP 1.2 7.5 mA
Standby mode, EN = Low, Bus dominant (total bus load, where RLIN ≥ 500 Ω and CLIN ≤ 10 nF (see Figure 9-1)(3), INH = VSUP, NWake = VSUP 1 2.1 mA
Normal mode, EN = High, Bus recessive, LIN = VSUP, INH = VSUP, NWake = VSUP 450 775 μA
Standby mode, EN = Low, Bus recessive, LIN = VSUP, INH = VSUP, NWake = VSUP 450 775
Sleep mode, EN = 0,
7 V < VSUP ≤ 12 V, LIN = VSUP,
NWake = VSUP		 15 30 μA
Sleep mode, EN = 0,
12 V < VSUP < 27 V, LIN = VSUP,
NWake = VSUP		 50 μA
RXD OUTPUT PIN
VO Output voltage –0.3 5.5 V
IOL Low-level output current, open drain LIN = 0 V, RXD = 0.4 V 3.5 mA
IIKG Leakage current, high-level LIN = VSUP, RXD = 5 V –5 0 5 μA
TXD INPUT PIN
VIL Low-level input voltage –0.3 0.8 V
VIH High-level input voltage 2 5.5
VIT Input threshold hysteresis voltage 30 500 mV
Pulldown resistor 125 350 800 kΩ
IIL Low-level input current TXD = Low –5 0 5 μA
LIN PIN (REFERENCED TO VSUP)
VOH High-level output voltage LIN recessive, TXD = High,
IO = 0 mA, VSUP = 14 V		 VSUP – 1 V
VOL Low-level output voltage LIN dominant, TXD = Low,
IO = 40 mA, VSUP = 14 V		 0 0.2 × VSUP V
RRESPONDER Pullup resistor to VSUP Normal and standby modes 20 30 60 kΩ
Pullup current source to VSUP Sleep mode, VSUP = 14 V, LIN = GND –2 –20 μA
IL Limiting current TXD = 0 V 45 160 250 mA
ILKG Leakage current LIN = VSUP –5 0 5 μA
ILKG Leakage current, loss of supply 7 V < LIN ≤ 12 V, VSUP = GND 5
12 V < LIN < 18 V, VSUP = GND 10
VIL Low-level input voltage LIN dominant 0.4 × VSUP V
VIH High-level input voltage LIN recessive 0.6 × VSUP
VIT Input threshold voltage 0.4 × VSUP 0.5 × VSUP 0.6 × VSUP
Vhys Hysteresis voltage 0.05 × VSUP 0.175 × VSUP
VIL Low-level input voltage for wake-up 0.4 × VSUP
EN PIN
VIL Low-level input voltage –0.3 0.8 V
VIH High-level input voltage 2 5.5
Vhys Hysteresis voltage 30 500 mV
Pulldown resistor 125 350 800 kΩ
IIL Low-level input current EN = Low –5 0 5 μA
INH PIN
Vo DC output voltage –0.3 VSUP + 0.3 V
Ron On state resistance Between VSUP and INH, INH = 2-mA drive, Normal or standby mode 35 85 Ω
IIKG Leakage current Low-power mode, 0 < INH < VSUP –5 0 5 μA
NWake PIN
VIL Low-level input voltage –0.3 VSUP – 3.3 V
VIH High-level input voltage VSUP – 1 VSUP + 0.3
Pullup current NWake = 0 V –45 –10 –2 μA
IIKG Leakage current VSUP = NWake –5 0 5
THERMAL SHUTDOWN
Thermal shutdown junction temperature 190 °C
AC CHARACTERISTICS
D1 Duty cycle 1(4) THREC(max) = 0.744 × VSUP, THDOM(max) = 0.581 × VSUP,
VSUP = 7 V to 18 V,
tBIT = 50 μs (20 kbps),
D1 = tBus_rec(min)/ (2 × tBIT).
See Figure 8-1		 0.396
D2 Duty cycle 2(4) THREC(min) = 0.422 × VSUP, THDOM(min) = 0.284 × VSUP,
VSUP = 7.6 V to 18 V,
tBIT = 50 μs (20 kbps),
D2 = tBus_rec(max)/ (2 × tBIT).
See Figure 8-1		 0.581
D3 Duty cycle 3(4) THREC(max) = 0.778 × VSUP, THDOM(max) = 0.616 × VSUP,
VSUP = 7 V to 18 V,
tBIT = 96 μs (10.4 kbps),
D3 = tBus_rec(min)/ (2 × tBIT).
See Figure 8-1		 0.417
D4 Duty cycle 4(4) THREC(min) = 0.389 × VSUP, THDOM(min) = 0.251 × VSUP,
VSUP = 7.6 V to 18 V,
tBIT = 96 μs (10.4 kbps),
D4 = tBus_rec(max)/ (2 × tBIT).
See Figure 8-1		 0.59
trx_pdr Receiver rising propagation delay time RRXD = 2.4 kΩ, CRXD = 20 pF
See Figure 8-2
See Figure 9-1		 6 μs
trx_pdf Receiver falling propagation delay time RRXD = 2.4 kΩ, CRXD = 20 pF
See Figure 8-2
See Figure 9-1		 6
trx_sym Symmetry of receiver propagation delay time rising edge with respect to falling edge (trx_sym = trx_pdf - trx_pdr)
RRXD = 2.4 kΩ, CRXD = 20 pF
See Figure 8-2
See Figure 9-1		 –2 2
tNWake NWake filter time for local wakeup See Figure 10-4 25 50 150
tLINBUS LIN wake-up filter time (dominant time for wakeup through LIN bus) See Figure 10-3 25 50 150
tDST Dominant state time-out(5) 5.5 20 ms
tgo_to_operate See Figure 10-2 to Figure 10-3 0.5 1 μs
(1) Typical values are given for VSUP = 14 V at 25°C, except for low power mode where typical values are given for VSUP = 12 V at 25°C.
(2) All voltages are defined with respect to ground; positive currents flow into the TPIC1021A device.
(3) In the dominant state, the supply current increases as the supply voltage increases due to the integrated LIN responder termination resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN responder termination is 20 kΩ, so the maximum supply current attributed to the termination is:
ISUP (dom) max termination ≉ (VSUP – (VLIN_Dominant + 0.7 V) / 20 kΩ
(4) Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are defined for 10.4-kbps operation. The TPIC1021A also meets these lower data rate requirements, while it is capable of the higher speed 20-kbps operation as specified by Duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle definitions, for details see the SAEJ2602 specification.
(5) Dominant state time-out limits the minimum data rate to 2.4 kbps.
GUID-F78BA79F-7BE3-4EDB-AF8F-5D39119E9E4A-low.gifFigure 8-1 Definition of Bus Timing Parameters
GUID-F5593BAE-ECAB-41E3-BCDE-73BD4BC5CCF2-low.gifFigure 8-2 Propagation Delay