SLIS110C April   2003  – March 2015 TPIC8101

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Functional Terminal Description
        1. 8.3.1.1  Supply Voltage (VDD)
        2. 8.3.1.2  Ground (GND)
        3. 8.3.1.3  Reference Supply (Vref)
        4. 8.3.1.4  Buffered Integrator Output (OUT)
        5. 8.3.1.5  Integration/Hold Mode Selection (INT/HOLD)
        6. 8.3.1.6  Chip Select for SPI (CS)
        7. 8.3.1.7  Oscillator Input (XIN)
        8. 8.3.1.8  Oscillator Output (XOUT)
        9. 8.3.1.9  Data Output (SDO)
        10. 8.3.1.10 Data Input (SDI)
        11. 8.3.1.11 Serial Clock (SCLK)
        12. 8.3.1.12 Test (TEST)
        13. 8.3.1.13 Feedback Output for Amplifiers (CH1FB and CH2FB)
        14. 8.3.1.14 Input Amplifiers (CH1P, CH1N, CH2P, and CH2N)
      2. 8.3.2 Timing Information
    4. 8.4 Device Functional Modes
      1. 8.4.1 System Transfer Equation
      2. 8.4.2 Programming in Normal Mode (TEST = 1)
      3. 8.4.3 Default SPI Mode
      4. 8.4.4 Advanced SPI Mode
      5. 8.4.5 Digital Data Output from the TPIC8101
    5. 8.5 Programming
      1. 8.5.1 Programming Examples
      2. 8.5.2 Programming in TEST Mode (TEST = 0)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The layout of the TPIC8101 can be routed as a two layer board, with the top layer primarily used for routing signals and the second layer used primarily as a ground plane.

The capacitors on VDD and VREF should be kept close to their respective pins and tie immediately through vias to ground. VREF should be connected to CH1P and CH2P in as tight a loop as possible. It can be routed on the second layer if necessary.

The resistor between Ch1N and CH1FB and CH2N and CH2FB should be kept close to the respective pins. The rest of the input signal chain should be routed cleanly to avoid noise interference.

The filter on XIN and XOUT for the input clock should be kept close to the XIN and XOUT pins.

11.2 Layout Example

TPIC8101 layout_ex_comp_LIS110.gifFigure 7. PCB Layout Example