SNAS806 September   2020 TPL1401

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Standard Mode
    7. 6.7  Timing Requirements: I2C Fast Mode
    8. 6.8  Timing Requirements: I2C Fast Mode Plus
    9. 6.9  Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    10. 6.10 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Potentiometer (Digipot) Architecture
        1. 7.3.1.1 Reference Selection and Digipot Transfer Function
          1. 7.3.1.1.1 Power Supply as Reference
          2. 7.3.1.1.2 Internal Reference
      2. 7.3.2 Digipot Update
      3. 7.3.3 Nonvolatile Memory (EEPROM or NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check
          1. 7.3.3.1.1 NVM_CRC_ALARM_USER Bit
          2. 7.3.3.1.2 NVM_CRC_ALARM_INTERNAL Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 Software Reset
      6. 7.3.6 Device Lock Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
    5. 7.5 Programming
      1. 7.5.1 F/S Mode Protocol
      2. 7.5.2 I2C Update Sequence
      3. 7.5.3 Address Byte
      4. 7.5.4 Command Byte
      5. 7.5.5 I2C Read Sequence
    6. 7.6 Register Map
      1. 7.6.1 STATUS Register (address = D0h) (reset = 000Ch or 0014h)
      2. 7.6.2 GENERAL_CONFIG Register (address = D1h) (reset = 01F0h)
      3. 7.6.3 PROTECT Register (address = D3h) (reset = 0008h)
      4. 7.6.4 DPOT_POSITION Register (address = 21h) (reset = 0000h)
      5. 7.6.5 USER_BYTE1 Register (address = 25h) (reset = 0000h)
      6. 7.6.6 USER_BYTE2 Register (address = 26h) (reset = 0000h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.11 Typical Characteristics

at TA = 25°C and digipot outputs unloaded (unless otherwise noted)

Reference = VDD
Figure 6-21 Integral Linearity Error
vs Supply Voltage
Reference = VDD
Figure 6-23 Total Unadjusted Error
vs Supply Voltage
Reference = VDD
Figure 6-25 Offset Error vs Supply Voltage
Reference = VDD
Figure 6-27 Full-Scale Error vs Supply Voltage
VDD = 5.5 V
Figure 6-29 Supply Current vs Digital Input Code
GUID-17940ACE-AD0B-4EFA-BB13-DF00019DE630-low.gif
Internal reference (gain = 4x), digipot at midscale
Figure 6-31 Supply Current vs Temperature
GUID-75CBB65C-CF33-4344-9D16-B5CE7F33A751-low.gif
Reference = VDD, digipot powered down
Figure 6-33 Power-Down Current vs Temperature
Reference = VDD = 5.5 V, digipot code transition from midscale to midscale + 1 LSB, digipot load = 5 kΩ || 200 pF
Figure 6-35 Glitch Impulse, Rising Edge,
1-LSB Step
Reference = VDD = 5.5 V, digipot load = 5 kΩ || 200 pF
Figure 6-37 Full-Scale Settling Time, Rising Edge
Reference = VDD = 5.5 V
Figure 6-39 Power-on Glitch
Reference = VDD = 5.5 V, fast mode plus, digipot at midscale, digipot load = 5 kΩ || 200 pF
Figure 6-41 Clock Feedthrough
Reference = VDD = 5.5 V
Figure 6-43 Output Noise Spectral Density
Reference = VDD = 5.5 V, digipot at midscale
Figure 6-45 Digipot Output Noise: 0.1 Hz to 10 Hz
Reference = VDD
Figure 6-22 Differential Linearity Error
vs Supply Voltage
Reference = VDD
Figure 6-24 Zero-Code Error
vs Supply Voltage
Reference = VDD
Figure 6-26 Gain Error vs Supply Voltage
VDD = 1.8 V
Figure 6-28 Supply Current vs Digital Input Code
GUID-BC89E4BF-D9CA-4E34-9EF6-EA4D344B5CC3-low.gif
Reference = VDD, digipot at midscale
Figure 6-30 Supply Current vs Temperature
Digipot at midscale
Figure 6-32 Supply Current vs Supply Voltage
GUID-7F146A73-1BDB-4844-847D-2B716E23CCF0-low.gif
 
Figure 6-34 Source and Sink Capability
Reference = VDD = 5.5 V, digipot code transition from midscale to midscale – 1 LSB, digipot load = 5 kΩ || 200 pF
Figure 6-36 Glitch Impulse, Falling Edge,
1-LSB Step
Reference = VDD = 5.5 V, digipot load = 5 kΩ || 200 pF
Figure 6-38 Full-Scale Settling Time, Falling Edge
Reference = VDD = 5.5 V
Figure 6-40 Power-off Glitch
GUID-A0B349D9-A4FD-4558-8D16-08EF35592A7D-low.gif
Internal reference (gain = 4x), VDD = 5.25 V + 0.25 VPP, digipot at midscale, digipot load = 5 kΩ || 200 pF
Figure 6-42 Output AC PSRR vs Frequency
Internal reference (gain = 4x), VDD = 5.5 V
Figure 6-44 Output Noise Spectral Density
Internal reference (gain = 4x), VDD = 5.5 V, digipot at midscale
Figure 6-46 Digipot Output Noise: 0.1 Hz to 10 Hz