SNAS806 September   2020 TPL1401

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Standard Mode
    7. 6.7  Timing Requirements: I2C Fast Mode
    8. 6.8  Timing Requirements: I2C Fast Mode Plus
    9. 6.9  Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    10. 6.10 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Potentiometer (Digipot) Architecture
        1. 7.3.1.1 Reference Selection and Digipot Transfer Function
          1. 7.3.1.1.1 Power Supply as Reference
          2. 7.3.1.1.2 Internal Reference
      2. 7.3.2 Digipot Update
      3. 7.3.3 Nonvolatile Memory (EEPROM or NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check
          1. 7.3.3.1.1 NVM_CRC_ALARM_USER Bit
          2. 7.3.3.1.2 NVM_CRC_ALARM_INTERNAL Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 Software Reset
      6. 7.3.6 Device Lock Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
    5. 7.5 Programming
      1. 7.5.1 F/S Mode Protocol
      2. 7.5.2 I2C Update Sequence
      3. 7.5.3 Address Byte
      4. 7.5.4 Command Byte
      5. 7.5.5 I2C Read Sequence
    6. 7.6 Register Map
      1. 7.6.1 STATUS Register (address = D0h) (reset = 000Ch or 0014h)
      2. 7.6.2 GENERAL_CONFIG Register (address = D1h) (reset = 01F0h)
      3. 7.6.3 PROTECT Register (address = D3h) (reset = 0008h)
      4. 7.6.4 DPOT_POSITION Register (address = 21h) (reset = 0000h)
      5. 7.6.5 USER_BYTE1 Register (address = 25h) (reset = 0000h)
      6. 7.6.6 USER_BYTE2 Register (address = 26h) (reset = 0000h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V, reference tied to VDD, gain = 1x, digipot output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution 8 Bits
INL Relative accuracy(1) –1 1 LSB
DNL Differential nonlinearity(1) –1 1 LSB
Zero code error Code 0d into digipot 6 12 mV
Internal VREF, gain = 4x, VDD = 5.5 V 6 15
Zero code error temperature coefficient ±10 µV/°C
Offset error VREF tied to VDD, measured between end-point codes 2d and 254d, output unloaded –0.5 0.25 0.5 %FSR
Offset error temperature coefficient VREF tied to VDD, measured between end-point codes 2d and 254d, output unloaded ±0.0003 %FSR/°C
Gain error VREF tied to VDD, measured between end-point codes 2d and 254d, output unloaded –0.5 0.25 0.5 %FSR
Gain error temperature coefficient VREF tied to VDD, measured between end-point codes 2d and 254d, output unloaded ±0.0008 %FSR/°C
Full scale error 1.8 V ≤ VDD < 2.7 V, code 511d into digipot,
no headroom		 –1 0.5 1 %FSR
2.7 V ≤ VDD ≤ 5.5 V, code 511d into digipot,
no headroom		 –0.5 0.25 0.5
Full scale error temperature coefficient ±0.0008 %FSR/°C
OUTPUT CHARACTERISTICS
Output voltage Reference tied to VDD 0 5.5 V
CL Capacitive load(2) RL = Infinite, phase margin = 30° 1 nF
RL = 5 kΩ, phase margin = 30° 2
Load regulation Digipot at midscale, –10 mA ≤ IOUT ≤ 10 mA,
VDD = 5.5 V		 0.4 mV/mA
Short circuit current VDD = 1.8 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD 		10 mA
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD 		25
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD 		50
Output voltage headroom(1) To VDD (digipot output unloaded, internal reference = 1.21 V), VDD ≥ 1.21 ☓ gain + 0.2 V 0.2 V
To VDD (digipot output unloaded) 0.8 %FSR
To VDD (ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V), digipot code = full scale 10
VOUT dc output impedance Digipot output enabled and digipot code = midscale 0.25 Ω
Digipot output enabled and digipot code = 2d 0.25
Digipot output enabled and digipot code = 254d 0.26
ZO VFB dc output impedance(3) Digipot output enabled 160 200 240 kΩ
VOUT + VFB dc output leakage(2) At start up, measured when digipot output is disabled and held at VDD / 2 for VDD = 5.5 V 5 nA
Power supply rejection ratio (dc) Internal VREF, gain = 2x, digipot at midscale;
VDD = 5 V ±10%		 0.25 mV/V
DYNAMIC PERFORMANCE
tsett Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V 8 µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V, internal VREF, gain = 4x 12
Slew rate VDD = 5.5 V 1 V/µs
Power on glitch magnitude At start up (buffer output disabled), RL = 5 kΩ,
CL = 200 pF		 75 mV
At start up (buffer output disabled), RL = 100 kΩ 200
Output enable glitch magnitude Buffer output disabled to enabled (digipot registers at zero scale, RL = 100 kΩ 250 mV
Vn Output noise voltage (peak to peak) 0.1 Hz to 10 Hz, digipot at midscale, VDD = 5.5 V 34 µVPP
Internal VREF, gain = 4x, 0.1 Hz to 10 Hz, digipot at midscale, VDD = 5.5 V 70
Output noise density Measured at 1 kHz, digipot at midscale, VDD = 5.5 V 0.2 µV/√Hz
Internal VREF, gain = 4x, measured at 1 kHz, digipot at midscale, VDD = 5.5 V 0.7
Power supply rejection ratio (ac)(3) Internal VREF, gain = 4x, 200-mV 50 or 60 Hz sine wave superimposed on power supply voltage, digipot at midscale –71 dB
Code change glitch impulse ±1 LSB change around mid code (including feedthrough) 10 nV-s
Code change glitch impulse magnitude ±1 LSB change around mid code (including feedthrough) 15 mV
VOLTAGE REFERENCE
Initial accuracy TA = 25°C 1.212 V
Reference output temperature coefficient(2) 50 ppm/°C 
EEPROM
Endurance –40°C ≤ TA ≤ 85°C  20000 Cycles
TA > 85°C 1000
Data retention(2) TA = 25°C  50 Years
EEPROM programming write cycle time(2) 10 20 ms
DIGITAL INPUTS
Digital feedthrough Digipot output static at midscale, fast mode plus, SCL toggling 20 nV-s
Pin capacitance Per pin 10 pF
POWER
Load capacitor - CAP pin(2) 0.5 15 µF
IDD Current flowing into VDD Normal mode, digipot at full scale, digital pins static 0.5 0.8 mA
Digipot power-down, internal reference power down 80 µA
(1) Measured with digipot output unloaded. For external reference between end-point codes 2d and 254d. For internal reference VDD ≥ 1.21 x gain + 0.2 V, between end-point codes 2d and 254d.
(2) Specified by design and characterization, not production tested.
(3) Specified with 200-mV headroom with respect to reference value when internal reference is used.