SNAS651A January 2015 – September 2018 TPL5010
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN(2) | TYP(3) | MAX(2) | UNIT | ||
---|---|---|---|---|---|---|---|
POWER SUPPLY | |||||||
IDD | Supply current(4) | Operation mode | 35 | 50 | nA | ||
Digital conversion of external resistance (Rext) | 200 | 400 | µA | ||||
TIMER | |||||||
tIP | Time Interval Period | 1650 selectable Time Intervals | Minimum time interval | 100 | ms | ||
Maximum time interval | 7200 | s | |||||
Time Interval Setting Accuracy(7) | Excluding the precision of Rext | ±0.6% | |||||
Timer Interval Setting Accuracy over supply voltage | 1.8 V ≤ VDD ≤ 5.5 V | ±25 | ppm/V | ||||
tOSC | Oscillator Accuracy | –0.5% | 0.5% | ||||
Oscillator Accuracy over temperature(5) | –40°C ≤ TA ≤ 105°C | ±100 | ±400 | ppm/°C | |||
Oscillator Accuracy over supply voltage | 1.8 V ≤ VDD ≤ 5.5 V | ±0.4 | %/V | ||||
Oscillator Accuracy over life time(6) | 0.24% | ||||||
tDONE | DONE Pulse width (5) | 100 | ns | ||||
tRSTn | RSTn Pulse width | 320 | ms | ||||
tWAKE | WAKE Pulse width | 20 | ms | ||||
t_Rext | Time to convert Rext | 100 | 120 | ms | |||
DIGITAL LOGIC LEVELS | |||||||
VIH | Logic High Threshold DONE pin | 0.7 × VDD | V | ||||
VIL | Logic Low Threshold DONE pin | 0.3 × VDD | V | ||||
VOH | Logic output High Level WAKE pin | Iout = 100 µA | VDD – 0.3 | V | |||
Iout = 1 mA | VDD – 0.7 | V | |||||
VOL | Logic output Low Level WAKE pin | Iout = -100 µA | 0.3 | V | |||
Iout = –1 mA | 0.7 | V | |||||
VOLRSTn | RSTn Logic output Low Level | IOL = –1 mA | 0.3 | V | |||
IOHRSTn | RSTn High Level output current | VOHRSTn = VDD | 1 | nA | |||
VIHM_RST | Logic High Threshold DELAY/M_RST pin | 1.5 | V |