SNAS681A February   2017  – September 2021 TPL5110-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DRV
      2. 7.3.2 DONE
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up
      2. 7.4.2 Timer Mode
      3. 7.4.3 One-Shot Mode
    5. 7.5 Programming
      1. 7.5.1 Configuring the Time Interval with the DELAY/M_DRV Pin
      2. 7.5.2 Manual MOSFET Power ON Applied to the DELAY/M_DRV Pin
        1. 7.5.2.1 DELAY/M_DRV
        2. 7.5.2.2 Circuitry
      3. 7.5.3 Selection of the External Resistance
      4. 7.5.4 Quantization Error
      5. 7.5.5 Error Due to Real External Resistance
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPL5110-Q1 Nano Timer is a low power, AEC-Q100 qualified timer with an integrated MOSFET driver ideal for power gating in duty cycled or battery powered applications. Consuming only 35nA, the TPL5110-Q1 can enable the power supply line and drastically reduce the overall system stand by current during the sleep time. Such power savings enable the use of significantly smaller batteries making it well suited for energy harvesting or wireless sensor applications. The TPL5110-Q1 provides selectable timing intervals from 100ms to 7200s and is designed for power gating applications. In addition, the TPL5110-Q1 has a unique One-shot feature where the timer will only power the MOSFET for one cycle. The TPL5110-Q1 is available in a 6-pin SOT23 package.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPL5110-Q1 SOT23 (6) 3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-943C45E2-9D66-49C9-8DFC-10479A2C1E6F-low.gif Simplified Application Schematic