SNAS650A JANUARY   2015  – September 2018 TPL5110

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DRV
      2. 7.3.2 DONE
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up
      2. 7.4.2 Timer Mode
      3. 7.4.3 One-Shot Mode
    5. 7.5 Programming
      1. 7.5.1 Configuring the Time Interval With the DELAY/M_DRV Pin
      2. 7.5.2 Manual MOSFET Power ON Applied to the DELAY/M_DRV Pin
        1. 7.5.2.1 DELAY/M_DRV
        2. 7.5.2.2 Circuitry
      3. 7.5.3 Selection of the External Resistance
      4. 7.5.4 Quantization Error
      5. 7.5.5 Error Due to Real External Resistance
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.5 Error Due to Real External Resistance

REXT is a theoretical value and may not be available in standard commercial resistor values. It is possible to closely approach the theoretical REXT using two or more standard values in parallel. However, standard values are characterized by a certain tolerance. This tolerance will affect the accuracy of the time interval.

The accuracy can be evaluated using the following procedure:

  1. Evaluate the min and max values of REXT (REXT_MIN, REXT_MAX with Equation 1 using the selected commercial resistance values and their tolerances.
  2. Evaluate the time intervals (TADC_MIN[REXT_MIN], TADC_MAX[REXT_MAX]) with the TADC equation mentioned in Equation 3.
  3. Find the errors using Equation 3 with TADC_MIN, TADC_MAX.
The results of the formula indicate the accuracy of the time interval.

The example below illustrates the procedure.

  • Desired time interval, T_desired = 600 s,
  • Required REXT from Equation 1, REXT= 57.44 kΩ.

From Table 3, REXT can be built with a parallel combination of two commercial values with 1% tolerance: R1 =1 07 kΩ, R2 = 124 kΩ. The uncertainty of the equivalent parallel resistance can be found using Equation 4:

Equation 4. TPL5110 uRp.gif

where

  • uRn (n=1,2) represent the uncertainty of a resistance (see Equation 5)

SPACER

Equation 5. TPL5110 uR.gif

The uncertainty of the parallel resistance is 0.82%, which means the value of REXT may range between REXT_MIN = 56.96 kΩ and REXT_MAX = 57.90 kΩ.

Using these value of REXT, the digitized timer intervals calculated by TADC equation mentioned in Equation 3 are respectively TADC_MIN = 586.85 s and TADC_MAX = 611.3 s, giving an error range of –1.88% / +2.19%. The asymmetry of the error range is due to the quadratic transfer function of the resistance digitizer.