SNAS659B June   2015  – September 2018 TPL5111

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DRVn
      2. 7.3.2 DONE
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up
      2. 7.4.2 Timer Mode
      3. 7.4.3 One-Shot Mode
    5. 7.5 Programming
      1. 7.5.1 Configuring the Time Interval With the DELAY/M_DRV Pin
      2. 7.5.2 Manual Power ON Applied to the DELAY/M_DRV Pin
        1. 7.5.2.1 DELAY/M_DRV
        2. 7.5.2.2 Circuitry
      3. 7.5.3 Selection of the External Resistance
      4. 7.5.4 Quantization Error
      5. 7.5.5 Error Due to Real External Resistance
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.2.1 DELAY/M_DRV

A resistance in the range between 500 Ω and 170 kΩ must to be connected to the DELAY/M_DRV pin to select a valid time interval. At POR and during the reading of REXT, the DELAY/M_DRV pin is internally connected to an analog signal chain through a multiplexer. After the reading of REXT, the analog circuit is switched off and the DELAY/M_DRV pin is internally connected to a digital circuit.

In this state, a logic HIGH applied to the DELAY/M_DRV pin is interpreted by the TPL5111 as a manual power ON. The manual power ON detection is provided with a de-bounce feature (on both edges) which makes the TPL5111 insensitive to the glitches on the DELAY/M_DRV.

The DELAY/M_DRV pin must stay HIGH for at least 20 ms to be valid. Once a valid signal at DELAY/M_DRV is understood as a manual power on, the DRVn signal will be asserted within the next 10 ms. Its duration will be according to the programmed time interval (minus 50 ms), or less if the DONE is received.

A manual power ON signal resets all the counters. The counters will restart as soon as a valid manual power ON signal is recognized and the signal at DELAY/M_DRV pin is asserted LOW. Due to the asynchronous nature of the manual power ON signal and its arbitrary duration, the HIGH status of the DRVn signal may have an uncertainty of about ±5 ms.

An extended assertion of a logic HIGH at the DELAY/M_DRV pin will turn on DRVn for a time longer than the programmed time interval. DONE signals received while the DELAY/M_DRV is HIGH are ignored. If the DRVn is already HIGH the manual power ON is ignored.