SNAS659B June   2015  – September 2018 TPL5111

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DRVn
      2. 7.3.2 DONE
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up
      2. 7.4.2 Timer Mode
      3. 7.4.3 One-Shot Mode
    5. 7.5 Programming
      1. 7.5.1 Configuring the Time Interval With the DELAY/M_DRV Pin
      2. 7.5.2 Manual Power ON Applied to the DELAY/M_DRV Pin
        1. 7.5.2.1 DELAY/M_DRV
        2. 7.5.2.2 Circuitry
      3. 7.5.3 Selection of the External Resistance
      4. 7.5.4 Quantization Error
      5. 7.5.5 Error Due to Real External Resistance
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics(1)

Specifications are for TA= 25°C, VDD-GND = 2.5 V, unless otherwise stated.
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
POWER SUPPLY
IDD Supply current(4) Operation mode 35 50 nA
Digital conversion of external resistance (Rext) 200 400 µA
TIMER
tIP Time interval Period 1650 selectable Time intervals Minimum time interval 100 ms
Maximum time interval 7200 s
Time interval Setting Accuracy(7) Excluding the precision of Rext ±0.6%
Time interval Setting Accuracy over supply voltage 1.8 V ≤ VDD ≤ 5.5 V ±25 ppm/V
tOSC Oscillator Accuracy –0.5% 0.5%
Oscillator Accuracy over temperature(5) –40°C ≤ TA≤ 105°C ±100 ±400 ppm/°C
Oscillator Accuracy over supply voltage 1.8 V ≤ VDD ≤ 5.5 V ±0.4 %/V
Oscillator Accuracy over life time(6) ±0.24%
tDONE DONE Pulse width (5) 100 ns
tDRVn DRVn Pulse width DONE signal not received tIP-50 ms
t_Rext Time to convert Rext 100 120 ms
DIGITAL LOGIC LEVELS
VIH Logic High Threshold DONE pin 0.7 × VDD V
VIL Logic Low Threshold DONE pin 0.3 × VDD V
VOH Logic output High Level DRVn pin Iout = 100 µA VDD – 0.3 V
Iout = 1 mA VDD – 0.7 V
VOL Logic output Low Level DRVn pin Iout = -100 µA 0.3 V
Iout = –1 mA 0.7 V
VIHM_DRV Logic High Threshold DELAY/M_DRV pin 1.5 V
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically.
(2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material.
(4) The supply current excludes load and pullup resistor current. Input pins are at GND or VDD.
(5) This parameter is specified by design and/or characterization and is not tested in production.
(6) Operational life time test procedure equivalent to10 years.
(7) The accuracy for time interval settings below 1second is ±10 0ms.