SLRS074 May   2018 TPL7407LA-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simple Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inductive Load Drive
      2. 7.4.2 Resistive Load Drive
      3. 7.4.3 ON State Input Current
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Unipolar Stepper Motor Driver
      2. 8.1.2 Multi-Purpose Sink Driver
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 TTL and other Logic Inputs
        2. 8.2.2.2 Input RC Snubber
        3. 8.2.2.3 High-Impedance Input Drivers
        4. 8.2.2.4 Drive Current
        5. 8.2.2.5 Output Low Voltage
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Improving Package Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Feature Description

Each channel of the TPL7407LA-Q1 consists of high power low side NMOS transistors driven by level shifting and gate driving circuitry. The gate drivers allow for high output current drive with a very low input voltage, meaning full operation with low GPIO voltages.

In order to enable floating inputs a 1-MΩ pull-down resistor exists on each channel. Another 50-kΩ resistor exists between the input and gate driving circuitry. This exists to limit the input current whenever there is an over voltage and the internal Zener clamps. It also interacts with the inherent capacitance of the gate driving circuitry to behave as an RC snubber to help prevent spurious switching in noisy environment.

In order to power the gate driving circuitry an LDO exists. See the Power Supply Recommendations section for further detail on this circuitry.

The diodes connected between the output and COM pin is used to suppress kick-back voltage from an inductive load that is excited when the NMOS drivers are turned off (stop sinking) and the stored energy in the coils causes a reverse current to flow into the coil supply.