This configurable use logic blocks can serve as either a 3-bit LUT, or as a D flip-flop/latch with a reset/set.

Figure 7-5 3-Bit LUT or DFF or Latch With nRST or nSET Block Diagram

When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection mux and produces a single output, which goes back into the connection mux. These LUTs can be configured to any 3-input user defined function, including the following standard digital logic functions: AND, NAND, OR, NOR, XOR, XNOR, INV.

Table 7-11 provides the truth table for a 3-bit LUT.

Each 3-bit LUT has 8 bits in the OTP to define their output function.

When used to implement a sequential logic element, the three input signals from the connection mux go to the data (D), clock (CLK), and reset/set (nRST/nSET) inputs for the flip-flop/latch, with the output going back to the connection mux. This macro-cell has initial state, clock polarity, reset/set polarity, and output polarity parameters.

The operation of the D flip-flop/latch will follow the following function descriptions:

• The clock polarity is configurable and can be set to non-inverted (CLKPOL = 0, CLK) or inverted (CLKPOL = 1, nCLK).
  • DFF with CLK: CLK is rising edge triggered, then Q = D; otherwise Q will not change.
  • DFF with nCLK: CLK is falling edge triggered, then Q = D; otherwise Q will not change.
  • Latch with CLK: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is High).
  • Latch with nCLK: when CLK is High, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is Low).
• These DFF/latches have an option for an active-low reset/set.
  • nRST: when the input is high, the DFF/latch is in normal operation; and when low, Q is reset to 0.
  • nSET: when the input is high, the DFF/latch is in normal operation; and when low, Q is set to 1.
• If reset/set is not desired, users may tie this input to V_CC or another constant high source.
• The output polarity is configurable and can be set to non-inverted (Q) or inverted (nQ).

Table 7-8 and Table 7-9 provides the truth tables for the D flip-flop and D latch with reset/set, respectively.