SCPS304 September   2024 TPLD1201-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT Macro-Cell
        2. 7.3.3.2 3-Bit LUT Macro-Cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell
      6. 7.3.6 Selectable Frequency Oscillator
      7. 7.3.7 Analog Comparators (ACMP)
      8. 7.3.8 Voltage Reference (VREF)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TPLD1201-Q1 DGS Package, 10-Pin VSSOP (Top View) Figure 4-1 DGS Package, 10-Pin VSSOP (Top View)
Table 4-1 Pin Functions
PIN DESCRIPTION
NAME

DGS

 TYPE(1)

Primary function

Secondary function (if any)
GPI

1

 I General-purpose input (2)
IO1

2

 I/O General-purpose I/O

ACMP0 IN+
IO2

3

 I/O General-purpose I/O

External VREF IN/ACMP0 or ACMP1 IN-
IO4

4

 I/O General-purpose I/O with output enable (OE)(3)

ACMP1 IN+
GND

5

P

 Ground
IO5

6

 I/O General-purpose I/O
IO6

7

 I/O General-purpose I/O
IO7

8

 I/O General-purpose I/O with output enable (OE).(3)

Internal VREF OUT

IO9

9

I/O

 General-purpose I/O External OSC IN

VCC

10

P

 Supply voltage
(1) P = power, I/O = input/output, I = Input
(2) The general-purpose input (GPI) pin will sustain a high-voltage (VPP) during programming. Take special precaution with peripherals connected to this pin if performing in-system programming.
(3) The output enable (OE) connection is available through the connection mux and can be configured in InterConnect Studio.