SCPS304 September   2024 TPLD1201-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT Macro-Cell
        2. 7.3.3.2 3-Bit LUT Macro-Cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell
      6. 7.3.6 Selectable Frequency Oscillator
      7. 7.3.7 Analog Comparators (ACMP)
      8. 7.3.8 Voltage Reference (VREF)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Analog Comparators (ACMP)

There are two analog comparator (ACMP) macro-cells in the TPLD1201-Q1. The analog comparator compares two voltages (IN+ and IN-) and outputs a digital signal (OUT) indicating which input is larger, a High signal for IN+ and a Low for IN-.

TPLD1201-Q1 ACMP Block DiagramFigure 7-19 ACMP Block Diagram

For the ACMP macro-cell to operate, the power up signal (PWR UP) needs to be asserted high. By connecting to signals coming from the connection mux, it is possible to have each ACMP always on, always off, or switched on dynamically based on a digital signal coming from the connection mux. When powered down, the ACMP will output a low signal.

  • PWR UP = 1: ACMP is powered up.
  • PWR UP = 0: ACMP is powered down.
Upon power-up, the ACMP output will remain low, and then become valid 100 μs (typical) after POR signal goes high. During this time, ensure the internal oscillator is not powered down.

Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources with a selectable gain stage before going into the analog comparator. ACMP1 also has a 100 µA pullup current source option for external sensor excitation purposes. The negative input signal is either created from an internal VREF or from an external source.

Table 7-15 ACMP0 and ACMP1 Input Sources
ParametersACMP0(1)ACMP1(2)
IN+ sourceAnalog Input 0 (shared with IO1)Analog Input 1 (shared with IO4)
VCCACMP0 IN+
IN- source50mV50mV
......
1200mV1200mV
VCC/3VCC/3
VCC/4VCC/4
VREF Analog Input (shared with IO2)VREF Analog Input (shared with IO2)
(1) Positive Analog input source to ACMP.
(2) Negative Analog input source to ACMP. Internal VREF thresholds are optimized near 1200mV.

IN+ gain: Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources, and can also have a selectable gain stage (1X, 0.5X, 0.33X, 0.25X) before connection to the analog comparator.

IN- voltage range: 50mV to 1.2V through the internal VREF, VCC/3, VCC/4, or external source.

Hysteresis: Each ACMP has four selectable hysteresis options 0mV, 25mV, 50mV and 200mV. The hysteresis is selectable if the internal VREF macro-cell or an external VREF input is used.

  • 0mV: will disable the input signal hysteresis.
  • 25mV: is a +12.5mV and -12.5mV hysteresis. For VREF = 1V, the trigger points will be 1.0125V and 0.9875V.
  • 50mV: is a +25mV and -25mV hysteresis. For VREF = 1V, the trigger points will be 1.025V and 0.975V.
  • 200mV: is a +100mV and -100mV hysteresis. For VREF = 1V, the trigger points will be 1.1V and 0.9V.
If hysteresis is desired, ensure the hysteresis is less than the VREF, otherwise the negative trigger point will be pushed below device ground which may stress the device beyond the Recommended Operating Conditions and reduce the lifetime of the device. For example, if VREF is set to 50mV and VHYS is 200mV, the trigger points will be 150mV and -50mV.

Low bandwidth: The ACMP cell has a selection for the bandwidth of the input signal, which can be used to save power and reduce noise impact when lower bandwidth signals are being compared.

If VCC/3 and VCC/4 are not used at ACMP negative input, they can be disabled to reduce power consumption.