SCPS304 September   2024 TPLD1201-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT Macro-Cell
        2. 7.3.3.2 3-Bit LUT Macro-Cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell
      6. 7.3.6 Selectable Frequency Oscillator
      7. 7.3.7 Analog Comparators (ACMP)
      8. 7.3.8 Voltage Reference (VREF)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4.2 Reset Counter Mode

When configured as a Counter (CNT) and a valid edge appears on the IN input, this macro-cells resets the internal counter to 0 and begins counting down from DATA on the next rising clock edge. Then, the macro-cell outputs a pulse for the duration of one CLK period when the count reaches 0 and wrap around to the value in DATA. The counter will continually operate until another reset is recevied. The edge on which the Counter is reset is determined by the Edge select parameter and can be configured as:

  • Rising: only rising edges of IN reset the counter.

  • Falling: only falling edges of IN reset the counter.

  • Both: both rising and falling edges of IN reset the counter.

  • High Level Reset: the counter is reset to 0 whenever IN is High; after reset, the counter output stays Low until the next rising CLK edge, then operates normally.

The counter time is calculated by COUNT = (DATA + 1)/fCLK. After a reset, an additional 2 clock cycles is added for clock synchronization, but there is an option to bypass the clock sync.

Note: Counters are initialized with DATA = 0 after POR.

Figure 7-13 and Figure 7-14 show examples of Counter output timing diagrams with respect to the Edge select parameter with DATA = 1 and DATA = 3, respectively.

TPLD1201-Q1 Counter output timing example (DATA = 1)Figure 7-13 Counter output timing example (DATA = 1)

TPLD1201-Q1 Counter output timing example (DATA = 3)Figure 7-14 Counter output timing example (DATA = 3)

Figure 7-15 shows an example of how the Counter macro-cell operates when the IN signal is shorter than the counter length (shown when edge select parameter is set to "both").

TPLD1201-Q1 Counter output timing example with RST < DATA (DATA = 3)Figure 7-15 Counter output timing example with RST < DATA (DATA = 3)