SCPS304 September   2024 TPLD1201-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT Macro-Cell
        2. 7.3.3.2 3-Bit LUT Macro-Cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell
      6. 7.3.6 Selectable Frequency Oscillator
      7. 7.3.7 Analog Comparators (ACMP)
      8. 7.3.8 Voltage Reference (VREF)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The TPLD1201-Q1 is part of the TI programmable logic device (TPLD) family of devices that feature versatile programmable logic ICs with combinational logic, sequential logic, and analog blocks to provide an integrated, compact, low power solution to implement common system functions.

The TPLD1201-Q1 has one GPI and seven GPIOs that can be configured as a digital input, digital output, digital input or output, or analog input or output.

The TPLD1201-Q1 has a system of interconnects, further referred to as the connection mux, to configure the routing of internal macro-cells and I/O pins. Each connection mux input is hardwired to a specific digital macro-cell output, such as digital I/O, lookup tables, and analog comparator outputs. The connection mux allows each of the digital inputs to only connect to one output so that bus contention does not occur.

The TPLD1201-Q1 features the following macro-cells:

  • Configurable use logic blocks:
    • Two 2-bit lookup tables (LUT)
    • Two 3-bit LUTs
    • Two 2-bit LUTs or D-type flip-flops (DFF) or latches
    • Two 3-bit LUTs or DFF or latches with reset/set option
    • One 3-bit LUT or Pipe delay
    • One 4-bit LUT or 8-bit counter (CNT) or delay generator (DLY)
  • Three 8-bit CNT/DLYs
  • One programmable deglitch filter (PFLT) or edge detector (EDET)
  • One oscillator (OSC) to generate either a 25kHz or 2MHz clock
  • Two analog comparators (ACMP)
  • Voltage reference (VREF) with option to output to analog IO

The InterConnect Studio software environment enables a simple drag-and-drop interface to build custom circuit designs and configure the macro-cells, I/O pins, and interconnections. In addition to circuit creation, InterConnect Studio has the ability to simulate digital and analog functionality to verify designs and provide a typical power consumption estimate. Once circuit designs are finalized, InterConnect Studio can temporarily emulate the design in the non-volatile memory or permanently program the one-time programmable (OTP). The OTP can be locked to prevent readback of its contents.