SCPS304
September 2024
TPLD1201-Q1
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Supply Current Characteristics
5.7
Switching Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
I/O Pins
7.3.2
Connection Mux
7.3.3
Configurable Use Logic Blocks
7.3.3.1
2-Bit LUT Macro-Cell
7.3.3.2
3-Bit LUT Macro-Cell
7.3.3.3
2-Bit LUT or D Flip-Flop or Latch Macro-Cell
7.3.3.4
3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell
7.3.3.5
3-Bit LUT or Pipe Delay Macro-cell
7.3.3.6
4-Bit LUT or 8-Bit Counter or Delay Macro-Cell
7.3.4
8-Bit Counters and Delay Generators (CNT/DLY)
7.3.4.1
Delay Mode
7.3.4.2
Reset Counter Mode
7.3.5
Programmable Deglitch Filter or Edge Detector Macro-cell
7.3.6
Selectable Frequency Oscillator
7.3.7
Analog Comparators (ACMP)
7.3.8
Voltage Reference (VREF)
7.4
Device Functional Modes
7.4.1
Power-On Reset
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Power Considerations
8.2.1.2
Input Considerations
8.2.1.3
Output Considerations
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Support Resources
9.3
Trademarks
9.4
Electrostatic Discharge Caution
9.5
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
11.1
Packaging Option Addendum
11.2
Tape and Reel Information
11.3
Mechanical Data
Package Options
Mechanical Data (Package|Pins)
DGS|10
MPDS035C
Thermal pad, mechanical data (Package|Pins)
Orderable Information
scps304_oa
7.2
Functional Block Diagram
Figure 7-1
TPLD1201-Q1
Functional Block Diagram