SCPS304 September   2024 TPLD1201-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT Macro-Cell
        2. 7.3.3.2 3-Bit LUT Macro-Cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell
      6. 7.3.6 Selectable Frequency Oscillator
      7. 7.3.7 Analog Comparators (ACMP)
      8. 7.3.8 Voltage Reference (VREF)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Supply and Power-on Reset
VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.71V to 5.5V 1.30 1.31 1.35 V
VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 1.71V to 5.5V 1.25 1.27 1.30 V
tSU Startup time from VCC rising past VPORR 1.71V to 5.5V 270 µs
VPP Programming voltage 7.5 8 8.5 V
Digital IO
VT+ Positive-going input threshold voltage Logic Input with Schmitt Trigger 1.8V ± 0.09V 0.94 1.27 V
3.3V ± 0.3V 1.55 2.17
5V ± 0.5V 2.21 3.19
VT- Negative-going input threshold voltage Logic Input with Schmitt Trigger 1.8V ± 0.09V 0.58 0.94 V
3.3V ± 0.3V 1.1 1.79
5V ± 0.5V 1.63 2.7
VHYS Schmitt trigger hysteresis (VT+ − VT−) Logic Input with Schmitt Trigger 1.8V ± 0.09V 0.25 0.47 V
3.3V ± 0.3V 0.33 0.54
5V ± 0.5V 0.42 0.66
VHYS GPI Hysteresis Voltage Hysteresis voltage applicable to the IN0 1.71V to 5.5V 0.2 V
VOH High-level output voltage Push-pull 1X or Open-drain PMOS 1X IOH = -100µA 1.8V ± 0.09V 1.68 V
Push-pull 2X or Open-drain PMOS 2X 1.69
Push-pull 1X or Open-drain PMOS 1X IOH = -3mA 3.3V ± 0.3V 2.60
Push-pull 2X or Open-drain PMOS 2X 2.75
Push-pull 1X or Open-drain PMOS 1X IOH = -5mA 5V ± 0.5V 3.99
Push-pull 2X or Open-drain PMOS 2X 4.16
VOL Low-level output voltage Push-pull 1X IOL = 100µA 1.8V ± 0.09V 0.01 V
Push-pull 2X 0.01
Open-drain NMOS 1X 0.01
Open-drain NMOS 2X 0.01
Push-pull 1X IOL = 3mA 3.3V ± 0.3V 0.1
Push-pull 2X 0.1
Open-drain NMOS 1X 0.1
Open-drain NMOS 2X 0.1
Push-pull 1X IOL = 5mA 5V ± 0.5V 0.12
Push-pull 2X 0.12
Open-drain NMOS 1X 0.12
Open-drain NMOS 2X 0.12
IOZ Off-state (high-Z state) output current IO1, IO2, IO5, IO6, IO9 VO = 0 to 5.5V µA
FOUT Max output frequency(1) Push-pull 1X or Push-pull 2X 15pF Load capacitance  1.8V ± 0.09V 5 MHz
3.3V ± 0.3V 12
5V ± 0.5V 12
Rpu(int) Internal pull-up resistance 1 MΩ
100 kΩ
10 kΩ
Rpd(int) Internal pull-down resistance 1 MΩ
100 kΩ
10 kΩ
CI Input pin capacitance each input pin VI = VCC or GND 1.71V to 5.5V 1.2 pF
CIO Input-output pin capacitance each I/O pin VIO = VCC or GND 1.71V to 5.5V 2.0 pF
Analog Comparator
tstart Start time ACMP power on
delay		 Bandgap always on 1.71V to 5.5V 150 µs
VAI Input voltage Positive input 1.71V to 5.5V 0 VCC V
Negative input 0 1.2
Voffset Input offset voltage TA = 25℃ VHYS = 0 mV, Gain = 1,
VREF= 50mV - 1200mV		 1.71V to 5.5V –6 6 mV
–40°C < TA ≤ 125°C –7 7
dVIO/dT Input offset voltage drift –40°C < TA ≤ 125°C VHYS = 0 mV, Gain = 1,
VREF= 50mV - 1200mV		 1.71V to 5.5V ±7 µV/ºC
IB Input bias current 1 µA
CID Input capacitance, differential 3 pF
CIM Input capacitance, common mode 3 pF
PROP Propagation delay,
response time		 Gain = 1,
Vref = 50mV - 1200mV,
Overdrive = 50mV		 Low to High, 
Low bandwidth enabled		 1.71V to 5.5V 2.5 µs
High to Low
Low bandwidth enabled		 2.5
Low to High, 
Low bandwidth disabled		 0.25
High to Low
Low bandwidth disabled		 0.25
Analog Comparator - Hysteresis
VHYS Built-in hysteresis VHYS = 25mV TA = 25℃ 1.71V to 5.5V 20 25 30 mV
-40ºC to 125ºC 18.75 25 31.25
VHYS = 50mV TA = 25℃ 40 50 60
-40ºC to 125ºC 37.5 50 62.5
VHYS = 200mV TA = 25℃ 160 200 240
-40ºC to 125ºC 150 200 250
Analog Comparator - Input Gain
Rsin Series input resistance Gain = 0.5 1.71V to 5.5V 1 MΩ
Gain = 0.33 0.75
Gain = 0.25 1
Gerr Gain error Gain = 0.5 1.71V to 5.5V -1 1 %
Gain = 0.33 -1.5 1.5
Gain = 0.25 -2 2
Voltage Reference
VREF VREF error TA = 25℃ VREF = 150mV - 300mV 1.71V to 5.5V -10.2 1 10.2 %
–40°C < TA ≤ 125°C -11 1 11
TA = 25℃ VREF = 350mV - 600mV -5 0.9 5
–40°C < TA ≤ 125°C -5.5 0.9 5.5
TA = 25℃ VREF = 650mV - 1000mV -3.3 0.9 3.3
–40°C < TA ≤ 125°C -4.3 0.9 4.3
TA = 25℃ VREF = 1050mV - 1200mV -3 0.85 3
–40°C < TA ≤ 125°C -5 0.85 5
VREF Internal VREF error TA = 25℃ VREF = 150mV - 300mV 1.71V to 5.5V -3.1 1 3.1 %
–40°C < TA ≤ 125°C -4.3 1 4.3
TA = 25℃ VREF = 350mV - 600mV -3 0.95 3
–40°C < TA ≤ 125°C -4 0.95 4
TA = 25℃ VREF = 650mV - 1000mV -2.5 0.9 2.5
–40°C < TA ≤ 125°C -4 0.9 4
TA = 25℃ VREF = 1050mV - 1200mV -2.3 0.85 2.3
–40°C < TA ≤ 125°C -3.7 0.85 3.7
ILOAD Output Current 1.71V to 5.5V 500 µA
dVOUT/dT Output voltage temperature drift 1.71V to 5.5V 550 ppm/ºC
dVOUT/dILOAD Load regulation 1.71V to 5.5V 0.1 1 mV/µA
(1) Open drain switching performance will be limited by pull-up resistors used