SCPS301 September   2024 TPLD801-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
  7. 6Parameter Measurement Information
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT macro-cell
        2. 7.3.3.2 3-Bit LUT macro-cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop/Latch macro-cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch with Set/Reset macro-cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter/Delay macro-cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell
      6. 7.3.6 Selectable Frequency Oscillator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 One-Time Programmable Memory (OTP)
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Option Addendum
    2. 9.2 Tape and Reel Information
    3. 9.3 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)

The counters/delay generators are 8-bit, supporting counter data values from 1 to 255. For flexibility, the clock source for each of these macro-cells can be configured as the internal oscillator, a divided clock derived from an oscillator (OSC/4, /12, /24, /64, /4096), or an external clock source coming from the connection mux. There is also the option to chain from the output of the previous CNT/DLY macro-cell to implement longer counter/delay circuits. Note that the counter/delay macro-cell is rising edge triggered, that is the counter will increment/decrement on rising clock edges.

TPLD801-Q1 CNT/DLY Block DiagramFigure 7-9 CNT/DLY Block Diagram
TPLD801-Q1 CNT/DLY3 Block DiagramFigure 7-10 CNT/DLY3 Block Diagram

As a counter/delay (CNT/DLY) macro-cell, users may select from the following modes: delay, counter.

DLY3 also has an optional edge detector that will generate a short pulse on the specified edge in addition to the delayed output.