SLUSEZ2 October   2023 TPS1210-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, G2, BST, SRC)
      2. 9.3.2 Capacitive Load Driving Using FET Gate (G1PU, G1PD) Slew Rate Control
      3. 9.3.3 Short-Circuit Protection
        1. 9.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 9.3.3.2 Short-Circuit Protection With Latch-Off
      4. 9.3.4 Undervoltage Protection (UVLO)
      5. 9.3.5 Reverse Polarity Protection
      6. 9.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 9.3.7 TPS1210x-Q1 as a Simple Gate Driver
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Application Limitations
        1. 10.1.1.1 Short-Circuit Protection Delay
        2. 10.1.1.2 Short-Circuit Protection Threshold
    2. 10.2 Typical Application: Circuit Breaker in Battery Management System (BMS) using Low Side Current Sense
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, G2, BST, SRC)

Figure 9-1 shows a simplified diagram of the charge pump and gate driver circuit implementation. The device houses two strong 1.69-A/2-A peak source/sink gate drivers enabling paralleling of FETs in high power system designs ensuring minimum transition time in saturation region. A 11-V, 345-µA charge pump is derived from VS terminal and charges the external boot-strap capacitor, CBST that is placed across the gate driver (BST and SRC).

VS is the supply pin to the controller. With VS applied and EN/UVLO pulled high, the charge pump turns ON and charges the CBST capacitor. After the voltage across CBST crosses V(BST_UVLOR), the GATE driver section is activated. The device has a 1-V (typical) UVLO hysteresis to ensure chattering less performance during initial GATE turn ON. Choose CBST based on the external FET QG and allowed dip during FET turn-ON. The charge pump remains enabled until the BST to SRC voltage reaches 11.8 V, typically, at which point the charge pump is disabled decreasing the current draw on the VS pin. The charge pump remains disabled until the BST to SRC voltage discharges to 10 V typically at which point the charge pump is enabled. The voltage between BST and SRC continue to charge and discharge between 11.8 V and 10 V as shown in the Figure 9-2.

GUID-20230423-SS0I-4P1H-L20N-Z8BM7KKKG9LW-low.svgFigure 9-1 Gate Drivers
GUID-20230423-SS0I-RJHB-TV47-JGLTDMSGT332-low.svgFigure 9-2 Charge Pump Operation

Use the following equation to calculate the initial gate driver enable delay:

Equation 1. TDRV_EN= CBST × V(BST_UVLOR)345 µA

Where,

CBST is the charge pump capacitance connected across BST and SRC pins.

V(BST_UVLOR) = 9.5 V (maximum).

If TDRV_EN must be reduced then pre-bias BST terminal externally using an external VAUX supply through a low leakage diode D1 as shown in . With this connection, TDRV_EN reduces to 400 µs. TPS12100-Q1 application circuit with external supply to BST is shown in Figure 9-3.

GUID-20230423-SS0I-1DMG-QXN6-C8ZH11V8TRGT-low.svg Figure 9-3 TPS12100-Q1 Application Circuit With External Supply to BST
Note:

VAUX can be supplied by external regulated supply ranging between 8 V and 18 V.