SLUSEZ2 October 2023 TPS1210-Q1
ADVANCE INFORMATION
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | TPS1210x-Q1 | ||
DGX-19 (VSSOP) | |||
EN/UVLO | 1 | I | EN/UVLO Input. A voltage on this pin above 1.21 V enables normal operation. Forcing this pin below 0.3 V shuts down the device reducing quiescent current to approximately 1.6 µA (typical). Optionally connect to the input supply through a resistive divider to set the undervoltage lockout. When EN/UVLO is left floating an internal pull down of 100 nA pulls EN/UVLO low and keeps the device in shutdown state. |
INP2 | 2 | I | Input Signal for external charge FET control. In TPS12100-Q1 drive INP2 high to drive G2 high. Drive INP2 low to pull G2 low. INP2 has an internal weak 100-nA pulldown to GND to keep G2 pulled low to SRC when INP2 is left floating. In TPS12101-Q1 drive INP2 low to drive G2 high. Drive INP2 high to pull G2 low. INP2 has an internal weak pulldown of 100 nA to GND to keep G2 high when INP2 is left floating. |
INP1 | 3 | I | Input Signal for external charge FET control. In TPS12100-Q1 drive INP1 high to drive G1PU high. Drive INP1 low to pull G1PD low. INP1 has an internal weak pulldown of 100 nA to GND to keep G1PD pulled to SRC when INP1 is left floating. In TPS12101-Q1, drive INP1 low to drive G1PU high. Drive INP1 high to pull G1PD low. INP1 has an internal weak pull down of 100 nA to GND to keep G1PU high when INP1 is left floating. |
N.C | 4 | — | No connect |
FLT | 5 | O | Open Drain Fault Output. This pin asserts low during short-circuit fault, charge pump UVLO, input UVLO and during SCP comparator diagnosis. If FLT feature is not desired then connect it to GND. |
GND | 6 | G | Connect GND to system ground |
CS_SEL | 7 | I | Current sense select input. Connect this pin to ground to activate high side current sense. Drive this pin to > 2 V to activate low side current sensing. CS_SEL has an internal weak pull down of 100 nA to GND. |
ISCP | 8 | I | Short-circuit detection setting. A resistor across
ISCP to GND sets the short circuit current comparator
threshold. |
TMR | 9 | I | Fault Timer Input. A
capacitor across TMR pin to GND sets the delay time for
short-circuit fault turn-off . Leave this pin open for fastest response setting. If short-circuit protection feature is not desired then connect CS+, CS–, VS pins together and connect ISCP, TMR pins to GND. |
SCP_TEST | 10 | I | Internal short-circuit comparator (SCP) diagnosis input. When SCP_TEST is driven low to high with INP1 pulled high, the internal SCP comparator operation is checked. FLT goes low and G1PD gets pulled to SRC if SCP comparator is functional.Connect SCP_TEST pin to GND if this feature is not desired. SCP_TEST has an internal weak pulldown of 100 nA to GND. |
G2 | 11 | O | Charging FET gate drive output. This pin has 1.69-A peak source and 2-A sink capacity. Leave the G2 pin floating if the G2 drive functionality is unused. |
BST | 12 | O | High Side Bootstrapped Supply. An external capacitor with a minimum value of > Qg(tot) of the external FET must be connected between this pin and SRC. |
SRC | 13 | O | Source connection of the external FET |
G1PD | 14 | O | High Current Gate Driver Pull-Down. This pin pulls down to SRC. For the fastest turn-off, tie this pin directly to the gate of the external high side MOSFET. |
G1PU | 15 | O | High Current Gate Driver Pull-Up. This pin pulls up to BST. Connect this pin to G1PD for maximum gate drive transition speed. A resistor can be connected between this pin and the gate of the external MOSFET to control the in-rush current during turn-on. |
CS- | 17 | I | Current sense negative input |
CS+ | 18 | I | Current sense positive input |
N.C | 19 | — | No connect |
VS | 20 | Power | Supply pin of the controller |