SLUSEQ9D July   2022  – April 2024 TPS1211-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 FET Gate Slew Rate Control
        2. 8.3.2.2 Using Precharge FET - (with TPS12111-Q1 Only)
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 Overcurrent Protection with Auto-Retry
        2. 8.3.3.2 Overcurrent Protection with Latch-Off
        3. 8.3.3.3 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 Overvoltage (OV) and Undervoltage Protection (UVLO)
      6. 8.3.6 Remote Temperature Sensing and Protection (DIODE)
      7. 8.3.7 Output Reverse Polarity Protection
      8. 8.3.8 TPS1211x-Q1 as a Simple Gate Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving Zonal Controller Loads on 12-V Line in Power Distribution Unit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application: Reverse Polarity Protection with TPS12110-Q1
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20220704-SS0I-RNKC-KPSG-B4TPNQR3F0VW-low.svgFigure 5-1 DGX Package,19-Pin VSSOP(Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME TPS12110-Q1 TPS12111-Q1 TPS12112-Q1
DGX-19 (VSSOP)
EN/UVLO 1 1 1 I EN/UVLO input. A voltage on this pin above 1.21 V enables normal operation. Forcing this pin below 0.3 V shuts down the TPS1211x-Q1, reducing quiescent current to approximately 0.9 µA (typical). Optionally connect to the input supply through a resistive divider to set the undervoltage lockout. When EN/UVLO is left floating an internal pulldown of 60 nA pulls EN/UVLO low and keeps the device in OFF state.
OV 2 — 2 I Adjustable overvoltage threshold input. Connect a resistor ladder from input supply, OV to GND. When the voltage at OVP exceeds the over voltage cutoff threshold then the PD is pulled down to SRC turning OFF the external FET. When the voltage at OV goes below OV falling threshold then PU gets pulled up to BST, turning ON the external FET.
OV must be connected to GND when not used. When OV is left floating an internal pulldown of 60 nA pulls OV low and keeps PU pulled up to BST.
INP_G — 2 — I Input signal. CMOS compatible input reference to GND that sets the state of G pin. INP_G has an internal pulldown to GND to keep G pulled to SRC when INP_G is left floating.
INP 3 3 3 I Input signal. CMOS compatible input reference to GND that sets the state of PD and PU pins. INP has an internal pulldown to GND to keep PD pulled to SRC when INP is left floating.
FLT_T 4 4 4 O Open drain fault output. This pin asserts low when overtemperature fault is detected.
FLT_I 5 5 5 O Open drain fault output. This pin asserts low after the voltage on the TMR pin has reached the fault threshold of 1.1V. this pin indicates the pass transistor is about to turn off due to an overcurrent condition. The FLT_I pin does not go to a high-impedance state until the overcurrent condition and the auto-retry time expire.
GND 6 6 6 G Connect GND to system ground.
IMON 7 7 7 O Analog current monitor output. This pin sources a scaled down ratio of current through the external current sense resistor RSNS. A resistor from this pin to GND converts current proportional to voltage. If unused, connect it to GND.
IWRN 8 8 8 I Overcurrent detection setting. A resistor across IWRN to GND sets the over current comparator threshold.
Connect IWRN to GND if over current protection feature is not desired.
TMR 9 9 9 I Fault timer input. A capacitor across TMR pin to GND sets the times for fault warning, fault turn-off (FLT_I) and retry periods.
Leave it open for fastest setting. Connect TMR to GND to disable overcurrent protection.
DIODE 10 10 10 I Diode connection for temperature sensing. Connect it to base and collector of an MMBT3904 NPN BJT. Connect DIODE to GND, if remote over temperature sensing and protection feature is not desired.
G — 11 — O GATE of external Precharge FET. Connect to the GATE of the external FET.
N.C 11 — 11 — No connect.
BST 12 12 12 O High-side bootstrapped supply. An external capacitor with a minimum value of > Qg(tot) of the external FET must be connected between this pin and SRC.
SRC 13 13 13 O Source connection of the external FET.
PD 14 14 14 O High current gate driver pulldown. This pin pulls down to SRC. For the fastest turn-off, tie this pin directly to the gate of the external high side MOSFET.
PU 15 15 15 O High current gate driver pullup. This pin pulls up to BST. Connect this pin to PD for maximum gate drive transition speed. A resistor can be connected between this pin and the gate of the external MOSFET to control the inrush current during turn-on.
CS- 17 17 17 I Current sense negative input.
CS+ 18 18 18 I Current sense positive input. Connect a 50 - 100-Ω resistor across CS+ to the external current sense resistor.
ISCP 19 19 19 I Short-circuit detection threshold setting. Connect ISCP to CS– if short-circuit protection is not desired.
VS 20 20 20 Power Supply pin of the controller.