SLUSF08A March   2024  – September 2024 TPS1213-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving
        1. 7.3.2.1 Using Low Power Bypass FET (G2 drive) for Load Capacitor Charging
        2. 7.3.2.2 Using Main FET (G1 Drive) Gate Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 State Transition Timing Diagram
      3. 7.4.3 Power Down
      4. 7.4.4 Shutdown Mode
      5. 7.4.5 Low Power Mode
      6. 7.4.6 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application 1: Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application 2: Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 8.3.1 Design Requirements
      2. 8.3.2 External Component Selection
      3. 8.3.3 Application Curves
    4. 8.4 TIDA-020065: Automotive Smart Fuse Reference Design Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup, Output Bulk Capacitor Charging, Bi-directional Current Sensing and Software I2t
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGX|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Switching Characteristics

TJ = –40 ℃ to +125℃. V(VS) = 12 V, V(BST – SRC) = 11 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tG1PU(INP_H) INP Turn ON propogation Delay INP ↑ to G1PU  ↑,  CL = 47 nF 0.45 1.53 µs
tG1PD(INP_L) INP Turn OFF propogation Delay INP ↓ to G1PD  ↓, CL = 47 nF 0.29 0.6 µs
tG2_ON(LPM) Active mode to LPM mode transition delay, G2 ON LPM ↓ to G2  ↑  6.4 µs
tG1_OFF(LPM) Active mode to LPM mode transition delay, G1 OFF LPM ↓, G2 ↑ (above V(G2_GOOD)) to G1  ↓, WAKE ↑,  CL(G1) = 47 nF 3.5 µs
tG2(WAKE_LPM) LPM Mode to Active mode transition delay with LPM trigger LPM ↑ , G1 ↑ (above V(G1_GOOD)) to G2  ↓, WAKE  ↓ , CL(G2) = 47 nF, V(LPM) = 0 V 6.6 µs
tG1(WAKE_LPM) LPM Mode to Active mode transition delay with LPM trigger LPM ↑ to G1  ↑,  CL = 47 nF 2 4.5 7.2 µs
tG2(WAKE_LWU) LPM Mode to Active mode transition delay (G2 OFF) during Load wakeup V(CS+–CS-)↑ V(SCP/LWU) , G1 ↑ (above V(G1_GOOD)) to G2  ↓, WAKE  ↓ , CL = 47 nF, V(LPM) = 0 V 6.9 µs
tG1(WAKE_LWU) LPM Mode to Active mode transition delay (G1 ON) during Load wakeup V(CS+–CS–)↑ V(SCP/LWU) to G1 ↑, CL = 47 nF, V(LPM) = 0 V 3 µs
tPD(EN_OFF) EN Turn OFF Propogation Delay  EN ↓ to G1PD  ↓, CL = 47 nF 2.2 4.6 6 µs
tPD(UVLO_OFF) UVLO Turn OFF Propogation Delay  UVLO ↓ to G1PD  ↓ and FLT ↓, CL = 47 nF 2.8 4.2 6 µs
tPD(VS_OFF) PD Turn OFF delay during input supply (VS) interruption VS ↓ (cross VPORF) to G1PD  ↓, CL = 47 nF, INP = EN/UVLO = 2 V 25 45.6 69.5 µs
tPU(VS_ON) PU Turn ON delay during input supply (VS) recovery VS ↑ (cross VPORR) to PU  ↑, CL = 47nF, INP = EN/UVLO = 2 V, V, V(BST–SRC) > V(BST_UVLOR) 220 657 µs
tSC Hard Short-circuit protection propogation delay V(CS+–CS–)↑ V(SCP/LWU) to G1PD ↓, CL = 47 nF, C(TMR) = Open, LPM = 2 V 4 µs
tSC_PUS Short-circuit protection propogation delay during power up with output short circuit CTMR = Open 10 µs
tPD(FLT_SC) FLT assertion delay during short circuit V(CS+–CS–)↑ V(SCP/LWU) to FLT  ↓, C(TMR) = Open 10.5 15 µs
FISCP ISCP Pulse current frequency 1.18 kHz
t(FLT_BSTUVLO) FLT assertion delay during Gate Drive UVLO V(BST–SRC) ↓ V(BST_UVLOF) to FLT ↓ 28 µs
t(FLT_BSTUVLO) FLT de-assertion delay during Gate Drive UVLO V(BST–SRC) ↑ V(BST_UVLOR) to FLT ↑ 17 µs