SLVSGF4B june   2022  – may 2023 TPS1641

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable and Shutdown Input (EN/SHDN)
      2. 8.3.2  Overvoltage Protection (OVP)
      3. 8.3.3  Output Slew Rate and Inrush Current Control (dVdt)
      4. 8.3.4  Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417
      5. 8.3.5  Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415
        1. 8.3.5.1 Internal Current Limit for the TPS16410 and TPS16411
      6. 8.3.6  Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads
      7. 8.3.7  Fast-Trip and Short-Circuit Protection
      8. 8.3.8  Analog Load Current Monitor (IMON) on the IOCP Pin
      9. 8.3.9  IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413)
      10. 8.3.10 Thermal Shutdown and Overtemperature Protection
      11. 8.3.11 Fault Response and Indication (FLT)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs)
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting Overvoltage Setpoints
        2. 9.2.2.2 Setting the Output Overcurrent Setpoint (IOCP)
        3. 9.2.2.3 Setting the Output Power Limit
        4. 9.2.2.4 Monitoring the Output Current
        5. 9.2.2.5 Limiting the Inrush Current and Setting the Output Slew Rate
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter
    4. 9.4 Best Design Practices
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Transient Protection
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Enable and Shutdown Input (EN/SHDN)

The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the quiescent current of the device is reduced to IQSD from Vcc supply.

While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is not in shutdown. See the Section 7.5 for VENR and VENF thresholds and the Section 7.6 for tLow_SHDN, tEN_OFF_dly, and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the device for fast turn-on and turn-off of internal FET. Figure 8-1 illustrates the EN/SHDN input in the TPS1641x devices. Figure 8-2 shows the start-up of the device with enable input.
GUID-20211220-SS0I-M4HM-HJPG-9HWNCJFTWJQJ-low.svg Figure 8-1 EN/SHDN in TPS1641x Devices
GUID-20220603-SS0I-HHKS-VWVT-ZHKZGRBFT10N-low.png
VIN = 12 V
Figure 8-2 Turn-On with Enable