SLVSG57 August   2021 TPS1653

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Hot Plug-In and In-Rush Current Control
        1. 8.3.1.1 Thermal Regulation Loop
      2. 8.3.2  Undervoltage Lockout (UVLO)
      3. 8.3.3  Overload and Short Circuit Protection
        1. 8.3.3.1 Overload Protection
        2. 8.3.3.2 Short Circuit Protection
          1. 8.3.3.2.1 Start-Up With Short-Circuit On Output
      4. 8.3.4  Current Monitoring Output (IMON)
      5. 8.3.5  FAULT Response (FLT)
      6. 8.3.6  Power Good Output (PGOOD)
      7. 8.3.7  IN, P_IN, OUT and GND Pins
      8. 8.3.8  Thermal Shutdown
      9. 8.3.9  Low Current Shutdown Control (SHDN)
      10. 8.3.10 Enable Input (EN)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Current-Limit Threshold R(ILIM) Selection
        2. 9.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 9.2.2.3 Setting Output Voltage Ramp Time (tdVdT)
          1. 9.2.2.3.1 Support Component Selections RPGOOD and C(IN)
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 48-V Power Amplifier Protection for Telecom Radios
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3.2 Short Circuit Protection

During a transient output short circuit event, the current through the device increases rapidly. As the current-limit amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip comparator. The fast-trip comparator architecture is designed for fast turn OFF tFASTTRIP(dly) = 1 µs (typical) with I(SCP) = 45 A of the internal FET during an output short circuit event. The fast-trip threshold is internally set to I(FASTTRIP). The fast-trip circuit holds the internal FET off for only a few microseconds, after which the device turns back on slowly, allowing the current-limit loop to regulate the output current to I(OL). Then the device functions similar to the overload condition. Figure 8-5 illustrates output hot-short performance of the device.

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VIN = 50 V RILIM = 18 kΩ
Figure 8-5 Output Hot-Short Response

The fast-trip comparator architecture has a supply line noise immunity resulting in a robust performance in noisy environments. This performance is achieved by controlling the turn OFF time of the internal FET based on the overcurrent level, I(FASTTRIP), through the device. The higher the overcurrent, the faster the turn OFF time, tFASTTRIP(dly). At Overload current level in the range of IFASTTRIP < IOUT < ISCP, the fast-trip comparator response is 3.2 µs (typical).