SLVSET9F September   2018  – February 2023 TPS1663

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Hot Plug-In and In-Rush Current Control
        1. 9.3.1.1 Thermal Regulation Loop
      2. 9.3.2  Undervoltage Lockout (UVLO)
      3. 9.3.3  Overvoltage Protection (OVP)
      4. 9.3.4  Overload and Short Circuit Protection
        1. 9.3.4.1 Overload Protection
        2. 9.3.4.2 Short Circuit Protection
          1. 9.3.4.2.1 Start-Up With Short-Circuit On Output
      5. 9.3.5  Output Power Limiting, PLIM (TPS16632 Only)
      6. 9.3.6  Current Monitoring Output (IMON)
      7. 9.3.7  FAULT Response (FLT)
      8. 9.3.8  Power Good Output (PGOOD)
      9. 9.3.9  IN, P_IN, OUT and GND Pins
      10. 9.3.10 Thermal Shutdown
      11. 9.3.11 Low Current Shutdown Control (SHDN)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Programming the Current-Limit Threshold R(ILIM) Selection
        2. 10.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 10.2.2.3 Setting Output Voltage Ramp Time (tdVdT)
          1. 10.2.2.3.1 Support Component Selections RPGOOD and C(IN)
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Simple 24-V Power Supply Path Protection
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Transient Protection
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
  • PWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.5 Output Power Limiting, PLIM (TPS16632 Only)

In TPS16630, with a fixed overcurrent limit threshold the maximum output power limit increases linearly with supply input. Electrical Industrial process control equipment such as PLC CPU must comply with standards like IEC61010-1 and UL1310 for fire safety which require limited energy and power circuits. Limiting the output power becomes a challenge in such high power applications where the operating supply voltage range is wide. The TPS16632 integrate adjustable output power limiting functionality that simplifies the system design requiring compliance in accordance to this standard.

Connect a resistor from PLIM to GND as shown in #T5006940-4N to set the output power limiting value. If output power limiting is not required, then connect PLIM to GND directly. This connection disables the PLIM functionality.

During an over-power load event, the TPS16632 limits the output power at the programmed value set by PLIM resistor. This limit indirectly results in the device operation in current limiting mode with steady state output voltage and current set by the load characteristics and PLIM = VOUT × IOUT. GUID-11039971-F80E-4560-8527-B1E4A4C9D168.html#PLIM_CURVE shows the output power limit and current limit characteristics of TPS16632 with 100-W power limit setting. The maximum duration for the device in power limiting mode is 162 msec (typical), tCL_PLIM(dly). After this time, the device operates either in auto-retry or latch off mode based on MODE pin configuration in Table 9-1.

Equation 5. P(PLIM) = 1 × R(PLIM)

Here, P(PLIM) is output power limit in watts, and R(PLIM) is the power limit setting resistor in kΩ.

During the output power limiting operation, FLT asserts after a delay of tCL_PLIM_FLT(dly). The FLT signal remains asserted until the over power load condition is removed and the device resumes normal operation.

#TESTX illustrates output power limiting performance of TPS16632 with 100-W setting for class-2 power supply designs .

GUID-5AAF1572-4316-4DF1-8598-2A51D6F2F541-low.gifFigure 9-10 TPS16632 Typical Application Schematic
GUID-DEF224D5-F4A1-403D-948C-0CAFF3ACF8A7-low.png
RPLIM = 100 kΩ RILIM = 3 kΩ
Figure 9-11 100 W class 2, Output Power Limiting Response of TPS16632