SLVSET9F September 2018 – February 2023 TPS1663
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The TPS1663x incorporate circuitry to protect the system during overvoltage conditions. The TPS16630 features an accurate ± 2% adjustable overvoltage cut off functionality. A voltage more than V(OVPR) on OVP pin turns off the internal FET and protects the downstream load. To program the OVP threshold externally, connect a resistor divider from IN supply to OVP terminal to GND as shown in GUID-EFA225D6-4B07-4237-99E9-57A72AEBFA09.html#T5464742-7. The TPS16632 features an internally fixed 39-V maximum overvoltage clamp V(OVC) functionality. The TPS16632 clamps the output voltage to V(OVC), when the input voltage exceeds 40 V. During the output voltage clamp operation, the power dissipation in the internal MOSFET is PD = (V(IN) – V(OVC)) × I(OUT). Excess power dissipation for a prolonged period can increase the device temperature. To avoid this, the internal FET is operated in overvoltage clamp for a maximum duration of tOVC(dly), 162 msec (typical). After this duration, the internal FET is turned OFF and the subsequent operation of the device depends on the MODE configuration (auto-retry or latch off) setting as per the Table 9-1.
#TESTD illustrates the overvoltage cut-off functionality and #TESTZ illustrates the overvoltage clamp functionality. FLT is asserted after a delay of 617 µs (typical) after entering in overvoltage clamp mode and remains asserted until the overvoltage fault is removed.
TPS16630 | OVP Setting at 33 V | |
TPS16632 | COUT = 10 µF, FLT connected to VOUT | RLOAD = 30 Ω |