SLVSET9F September 2018 – February 2023 TPS1663
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
UVLO INPUT (UVLO) | ||||||
UVLO_ton(dly) | UVLO switch turnon delay | UVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV, C(dVdT) ≥ 10 nF, [C(dVdT) in nF] | 742 + 49.5 x C(dVdT) | µs | ||
UVLO_toff(dly) | UVLO switch turnoff delay | UVLO↓(20 mV below V(UVLOF)) to FLT↓ | 9 | 11 | 16 | µs |
tUVLO_FLT(dly) | UVLO to Fault de-assertion delay | UVLO↑ to FLT ↑ delay | 500 | 617 | 700 | µs |
OVER VOLTAGE PROTECTION INPUT (OVP) | ||||||
OVP_toff(dly) | OVP switch turnOFF delay | OVP↑ (20 mV above V(OVPR)) to FLT↓ | 8.5 | 11 | 14 | µs |
OVP_ton(dly) | OVP switch disable delay | OVP↓ (100 mV below V(OVPF)) to FET ON , C(dVdT) ≥ 10 nF, [C(dVdT) in nF] | 150 + 49.5 x C(dVdT) | µs | ||
tOVC(dly) | Maximum duration in over voltage clamp operation | TPS16632 only | 162 | ms | ||
OVC_tFLT(dly) | FLT assertion delay in over voltage clamp operation | TPS16632 only | 617 | µs | ||
SHUTDOWN CONTROL INPUT ( SHDN) | ||||||
tSD(dly) | SHUTDOWN entry delay | SHDN↓ (below V(SHUTF)) to FET OFF | 0.8 | 1 | 1.5 | µs |
CURRENT LIMIT | ||||||
tFASTTRIP(dly) | Hot-short response time | I(OUT) > I(SCP) | 1 | µs | ||
Soft short response | I(FASTTRIP) < I(OUT) < I(SCP) | 2.2 | 3.2 | 4.5 | µs | |
tCL_PLIM(dly) | Maximum duration in current & (power limiting: TPS16632 Only) | 129 | 162 | 202 | ms | |
tCL_PLIM_FLT(dly) | FLT delay in current & (power limiting: TPS16632 Only) | 1.09 | 1.3 | 1.6 | ms | |
OUTPUT RAMP CONTROL (dVdT) | ||||||
t(FASTCHARGE) | Output ramp time in fast charging | C(dVdT) = Open, 10% to 90% V(OUT), C(OUT) = 1 µF; V(IN) = 24V | 350 | 495 | 700 | µs |
t(dVdT) | Output ramp time | C(dVdT) = 22 nF, 10% to 90% V(OUT), V(IN) = 24 V | 8.35 | ms | ||
POWER GOOD (PGOOD) | ||||||
tPGOODR | PGOOD delay (deglitch) time | Rising edge | 8 | 11.5 | 13 | ms |
tPGOODF | PGOOD delay (deglitch) time | Falling edge | 8 | 10 | 13 | ms |
THERMAL PROTECTION | ||||||
t(TSD_retry) | Retry delay in TSD | MODE = GND | 500 | 648 | 800 | ms |
t(Treg_timeout) | Thermal Regulation Timeout | 1.1 | 1.25 | 1.5 | s |