SLVSHA1 September   2024 TPS1685

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Logic Interface
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Protection
      2. 7.3.2  Insertion Delay
      3. 7.3.3  Overvoltage Protection
      4. 7.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 7.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 7.3.4.1.1 Start-Up Time Out
        2. 7.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 7.3.4.3 Active Current Limiting During Start-Up
        4. 7.3.4.4 Short-Circuit Protection
      5. 7.3.5  Analog Load Current Monitor (IMON)
      6. 7.3.6  Mode Selection (MODE)
      7. 7.3.7  Parallel Device Synchronization (SWEN)
      8. 7.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 7.3.8.1 Current Balancing During Start-Up
      9. 7.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 7.3.10 Overtemperature Protection
      11. 7.3.11 Fault Response and Indication (FLT)
      12. 7.3.12 Power Good Indication (PG)
      13. 7.3.13 Output Discharge
      14. 7.3.14 FET Health Monitoring
      15. 7.3.15 Single Point Failure Mitigation
        1. 7.3.15.1 IMON Pin Single Point Failure
        2. 7.3.15.2 IREF Pin Single Point Failure
        3. 7.3.15.3 ITIMER Pin Single Point Failure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Single Device, Standalone Operation
      2. 8.1.2 Multiple Devices, Parallel Connection
    2. 8.2 Typical Application: 54V Power Path Protection in Data Center Servers
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Transient Protection
      2. 8.3.2 Output Short-Circuit Measurements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
  • VMA|23
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Parallel Device Synchronization (SWEN)

The SWEN pin is a signal which is driven high when the FET must be turned ON. When the SWEN pin is driven low (internally or externally), it signals the driver circuit to turn OFF the FET. This pin serves both as a control and handshake signal and allows multiple devices in a parallel configuration to synchronize their FET ON and OFF transitions.

Table 7-2 SWEN Summary

Device State

FET Driver Status

SWEN

Steady-state

ON

H

Inrush

ON

H

Overtemperature shutdown

OFF

L

Auto-retry timer running

OFF

L

Undervoltage (EN/UVLO)

OFF

L

Undervoltage (VDD UVP)

OFF

L

Undervoltage (VIN UVP)

OFF

L

Insertion delay

OFF

L

Overvoltage lockout (VIN OVP)

OFF

L

Transient overcurrent

ON

H

Circuit-breaker (persistent overcurrent followed by ITIMER expiry)

OFF

L

Fast-trip

OFF

L

Fault response mono-shot running (MODE = GND)

OFF

L

Fault response mono-shot expired (MODE = GND)

ON

H

IMON pin open (steady-state)

OFF

L

IMON pin short (steady-state)

OFF

L

FET health fault

OFF

L
Note:

  1. The SWEN is an open-drain pin but has a weak internal pullup to VINT.

  2. The SWEN can also be pulled up to an external supply. TI recommends to use a system standby rail which is derived from the input of the eFuse.

In a primary + secondary parallel configuration, the SWEN pin is used by the primary device to control the on and off transitions of the secondary devices. At the same time, it allows the secondary devices to communicate any faults or other condition which can prevent it from turning on to the primary device. Refer to Fault Response and Indication (FLT) for more details.

To maintain state machine synchronization, the devices rely on SWEN level transitions as well as timing for handshakes. This ensures all the devices turn ON and OFF synchronously and in the same manner (for example, DVDT controlled or current limited start-up). There are also fail-safe mechanisms in the SWEN control and handshake logic to ensure the entire chain is turned off safely even if the primary device is unable to take control in case of a fault.

Note:

TI recommends to keep the parasitic loading on the SWEN pin to a minimum to avoid synchronization timing issues.