SLVSHA1 September   2024 TPS1685

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Logic Interface
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Protection
      2. 7.3.2  Insertion Delay
      3. 7.3.3  Overvoltage Protection
      4. 7.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 7.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 7.3.4.1.1 Start-Up Time Out
        2. 7.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 7.3.4.3 Active Current Limiting During Start-Up
        4. 7.3.4.4 Short-Circuit Protection
      5. 7.3.5  Analog Load Current Monitor (IMON)
      6. 7.3.6  Mode Selection (MODE)
      7. 7.3.7  Parallel Device Synchronization (SWEN)
      8. 7.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 7.3.8.1 Current Balancing During Start-Up
      9. 7.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 7.3.10 Overtemperature Protection
      11. 7.3.11 Fault Response and Indication (FLT)
      12. 7.3.12 Power Good Indication (PG)
      13. 7.3.13 Output Discharge
      14. 7.3.14 FET Health Monitoring
      15. 7.3.15 Single Point Failure Mitigation
        1. 7.3.15.1 IMON Pin Single Point Failure
        2. 7.3.15.2 IREF Pin Single Point Failure
        3. 7.3.15.3 ITIMER Pin Single Point Failure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Single Device, Standalone Operation
      2. 8.1.2 Multiple Devices, Parallel Connection
    2. 8.2 Typical Application: 54V Power Path Protection in Data Center Servers
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Transient Protection
      2. 8.3.2 Output Short-Circuit Measurements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
  • VMA|23
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.11 Fault Response and Indication (FLT)

Table 7-4 summarizes the device response to various fault conditions.

Table 7-4 Fault Summary

Event or Condition

Device Response

Fault Latched Internally

FLT Pin Status

Delay

Steady-state

None

N/A

H

Inrush

None

N/A

H

Overtemperature

Shutdown

Y

L

Undervoltage (EN/UVLO)

Shutdown

N

H

Undervoltage (VDD UVP)

Shutdown

N

H

Undervoltage (VIN UVP)

Shutdown

N

H

Overvoltage (VIN OVP)

Shutdown

N

H

Transient overcurrent

None

N

H

Persistent overcurrent (steady-state)

Circuit-Breaker

Y

L

tITIMER

Persistent overcurrent (start-up)

Current Limit

N

L

Short-circuit (primary mode)

Fast-trip

Y

L

tFT

Short-circuit (secondary mode)

Fast-trip followed by current limited Start-up

N

H

ILIM pin open (steady-state)

Active current sharing loop always active

N

H

ILIM pin short (steady-state)

Active current sharing loop disabled

N

H

IMON pin open (steady-state)

Shutdown

Y

L

IMON pin short (steady-state)

Shutdown (If IOUT > IOC_BKP)

Y

L

30

μs

IREF pin open (steady-state)

Shutdown (if IOUT > IOC_BKP)

Y

L

tITIMER

IREF pin short (steady-state)

Shutdown

Y

L

ITIMER pin forced to high voltage

Shutdown (if IOUT > IOCP or IOUT > IOC_BKP)

Y

L

tSPFAIL_TMR

Start-up timeout

Shutdown

Y

L

tSU_TMR

FET health fault (G-S)

Shutdown

Y

L

10 μs

FET health fault (G-D)

Shutdown

Y

L

FET health fault (D-S)

Shutdown

N

L

tSU_TMR

External fault (SWEN pulled low externally while device is not in UV or OV)

Shutdown

Y

L

FLT is an open-drain pin and must be pulled up to an external supply.

The device response after a fault varies based on the mode of operation:

  1. During standalone or primary mode of operation (MODE = OPEN), the device latches a fault and follows the auto-retry or latch-off response as per the device selection. When the device turns on again, it follows the usual DVDT limited start-up sequence.
  2. During the secondary mode of operation (MODE = GND), if the device detects any fault, it pulls the SWEN pin low momentarily to signal the event to the primary device and thereafter relies on the primary to take control of the fault response. However, if the primary device fails to register the fault, there i a failsafe mechanism in the secondary device to turn off the entire chain and enter a latch-off condition. Thereafter, the device can be turned on again only by power cycling VDD below VUVP(F) or by cycling EN/UVLO pin below VSD(F).

For faults that are latched internally, power cycling the part or pulling the EN/UVLO pin voltage below VSD(F) clears the fault and the pin is de-asserted. This action also clears the tRST timer (auto-retry variants only). Pulling the EN/UVLO just below the UVLO threshold has no impact on the device in this condition. This is true for both latch-off and auto-retry variants.