SLVSCM2D October   2014  – December 2019 TPS1H100-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements – Current Sense Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Accurate Current Sense
      2. 7.3.2 Programmable Current Limit
      3. 7.3.3 Inductive-Load Switching-Off Clamp
      4. 7.3.4 Full Protections and Diagnostics
        1. 7.3.4.1  Short-to-GND and Overload Detection
        2. 7.3.4.2  Open-Load Detection
        3. 7.3.4.3  Short-to-Battery Detection
        4. 7.3.4.4  Reverse-Polarity Detection
        5. 7.3.4.5  Thermal Protection Behavior
        6. 7.3.4.6  UVLO Protection
        7. 7.3.4.7  Loss of GND Protection
        8. 7.3.4.8  Loss of Power Supply Protection
        9. 7.3.4.9  Reverse Current Protection
        10. 7.3.4.10 Protection for MCU I/Os
      5. 7.3.5 Diagnostic Enable Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Working Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Distinguishing of Different Fault Modes
        2. 8.2.2.2 AEC Q100-012 Test Grade A Certification
        3. 8.2.2.3 EMC Transient Disturbances Test
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Without a GND Network
      2. 10.2.2 With a GND Network
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Inductive-Load Switching-Off Clamp

When an inductive load is switching off, the output voltage is pulled down to negative, due to the inductance characteristics. The power FET may break down if the voltage is not clamped during the current-decay period. To protect the power FET in this situation, internally clamp the drain-to-source voltage, namely VDS,clamp, the clamp diode between the drain and gate.

Equation 3. TPS1H100-Q1 eq_03_lvscm2.gif

During the current-decay period (TDECAY), the power FET is turned on for inductance-energy dissipation. Both the energy of the power supply (EBAT) and the load (ELOAD) are dissipated on the high-side power switch itself, which is called EHSD. If resistance is in series with inductance, some of the load energy is dissipated in the resistance.

Equation 4. TPS1H100-Q1 eq_04_lvscm2.gif

From the high-side power switch’s view, EHSD equals the integration value during the current-decay period.

Equation 5. TPS1H100-Q1 eq_05_lvscm2.gif
Equation 6. TPS1H100-Q1 eq_06_lvscm2.gif
Equation 7. TPS1H100-Q1 eq_07_lvscm2.gif

When R approximately equals 0, EHSD can be given simply as:

Equation 8. TPS1H100-Q1 eq_08_lvscm2.gif
TPS1H100-Q1 sch_01_lvscm2.gifFigure 32. Driving Inductive Load
TPS1H100-Q1 tim_t_decay_lvscm2.gifFigure 33. Inductive-Load Switching-Off Diagram

As discussed previously, when switching off, battery energy and load energy are dissipated on the high-side power switch, which leads to the large thermal variation. For each high-side power switch, the upper limit of the maximum safe power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation condition. TI provides the upper limit of single-pulse energy that devices can tolerate under the test condition: VVS = 13.5 V, inductance from 0.1 mH to 400 mH, R = 0 Ω, FR4 2s2p board, 2- × 70-μm copper, 2- × 35-μm copper, thermal pad copper area 600 mm2.

For one dedicated inductance, see Figure 34. If the maximum switching-off current is lower than the current value shown on the curve, the internal clamp function can be used for the demagnetization energy dissipation. If not, external free-wheeling circuitry is necessary for device protection.

TPS1H100-Q1 D026_SLVSCM2.gif
Figure 34. Maximum Current vs Inductance Range