SLVSCM2D October   2014  – December 2019 TPS1H100-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements – Current Sense Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Accurate Current Sense
      2. 7.3.2 Programmable Current Limit
      3. 7.3.3 Inductive-Load Switching-Off Clamp
      4. 7.3.4 Full Protections and Diagnostics
        1. 7.3.4.1  Short-to-GND and Overload Detection
        2. 7.3.4.2  Open-Load Detection
        3. 7.3.4.3  Short-to-Battery Detection
        4. 7.3.4.4  Reverse-Polarity Detection
        5. 7.3.4.5  Thermal Protection Behavior
        6. 7.3.4.6  UVLO Protection
        7. 7.3.4.7  Loss of GND Protection
        8. 7.3.4.8  Loss of Power Supply Protection
        9. 7.3.4.9  Reverse Current Protection
        10. 7.3.4.10 Protection for MCU I/Os
      5. 7.3.5 Diagnostic Enable Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Working Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Distinguishing of Different Fault Modes
        2. 8.2.2.2 AEC Q100-012 Test Grade A Certification
        3. 8.2.2.3 EMC Transient Disturbances Test
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Without a GND Network
      2. 10.2.2 With a GND Network
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Thermal Information

THERMAL METRIC(1) TPS1H100-Q1 UNIT
PWP (HTSSOP)
14 PINS
RθJA Junction-to-ambient thermal resistance (2) 41 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 29.7 °C/W
RθJB Junction-to-board thermal resistance 25.1 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 24.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The thermal data is based on JEDEC standard high-K profile – JESD 51-7. The copper pad is soldered to the thermal land pattern. Also, correct attachment procedure must be incorporated.
TPS1H100-Q1 D025_SLVSCM2.gif
1. 4-layer board: FR4 2s2p board, 2.8-mil copper (top/bottom), 1.4-mil copper (internal layers). 76.4- × 114.3- × 1.5-mm board size.
2. 2-layer board: FR4 2s0p board, 2.8-mil copper (top/bottom). 76.4- × 114.3- × 1.5-mm board size.
Figure 1. RθJA Value vs Copper Area