SLVSE18B June 2019 – February 2023 TPS1HB35-Q1
PRODUCTION DATA
All timing diagrams assume that the SEL1 pin is low.
The LATCH, DIA_EN, and EN pins are controlled by the user. The timing diagrams represent a possible use-case.
#SLVSE157371 shows the immediate current limit switch off behavior. The diagram also illustrates the retry behavior. As shown, the switch will remain latched off until the LATCH pin is low.
#SLVSE156584 shows the immediate current limit switch off behavior. In this example, LATCH is tied to GND; hence, the switch will retry after the fault is cleared and tRETRY has expired.
#SLVSDZ36421 shows the active current behavior of version C. In version C, the switch will not shutdown until thermal shutdown is reached.
#SLVSDZ33291 shows the active current behavior of version C. The switch will not shutdown until thermal shutdown is tripped. In this example, LATCH is tied to GND.
When the switch retries after a shutdown event, the SNS fault indication will remain until VOUT has risen to VBB – 1.8 V. After VOUT has risen, the SNS fault indication is reset and current sensing is available. If there is a short-to-ground and VOUT is not able to rise, the SNS fault indication will remain indefinitely. #SLVSE158822 illustrates auto-retry behavior and provides a zoomed-in view of the fault indication during retry.
#SLVSE158822 assumes that tRETRY has expired by the time that TJ reaches the hysteresis threshold.
LATCH = 0 V and DIA_EN = 5 V