SLVSFI1A July   2021  – December 2021 TPS1HC100-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Accurate Current Sense
      2. 8.3.2 Programmable Current Limit
        1. 8.3.2.1 Capacitive Charging
      3. 8.3.3 Inductive-Load Switching-Off Clamp
      4. 8.3.4 Full Protections and Diagnostics
        1. 8.3.4.1  Short-Circuit and Overload Protection
        2. 8.3.4.2  Open-Load and Short-to-Battery Detection
        3. 8.3.4.3  Short-to-Battery Detection
        4. 8.3.4.4  Reverse-Polarity and Battery Protection
        5. 8.3.4.5  Latch-Off Mode
        6. 8.3.4.6  Thermal Protection Behavior
        7. 8.3.4.7  UVLO Protection
        8. 8.3.4.8  Loss of GND Protection
        9. 8.3.4.9  Loss of Power Supply Protection
        10. 8.3.4.10 Reverse Current Protection
        11. 8.3.4.11 Protection for MCU I/Os
      5. 8.3.5 Diagnostic Enable Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Dynamically Changing Current Limit
        2. 9.2.2.2 AEC Q100-012 Test Grade A Certification
        3. 9.2.2.3 EMC Transient Disturbances Test
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Without a GND Network
      2. 11.2.2 With a GND Network
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.3 EMC Transient Disturbances Test

Due to the severe electrical conditions in the automotive environment, immunity capacity against electrical transient disturbances is required, especially for a high-side power switch, which is connected directly to the battery. Detailed test requirements are in accordance with the ISO 7637-2:2011 and ISO 16750-2:2010 standards. The TPS1HC100-Q1 device is tested and certificated by a third-party organization.

Table 9-4 ISO 7637-2:2011(E) in 12-V System(1)(2)(3)(4)
Test Item Test Pulse Severity Level and vs Accordingly Pulse Duration (td) Minimum Number of Pulses or Test Time Burst-Cycle Pulse-Repetition Time Input Resistance (Ω) Function Performance Status Classification
Level Vs/V MIN MAX
1 III –112 2 ms 500 pulses 0.5 s e s 10 Status II
2a III 55 50 µs 500 pulses 0.2 s 5 s 2 Status II
2b IV 10 0.2 to 2 s 10 pulses 0.5 s 5 s 0 to 0.05 Status II
3a IV –220 0.1 µs 1h 90 ms 100 ms 50 Status II
3b IV 150 0.1 µs 1h 90 ms 100 ms 50 Status II
(1) Tested both under input low condition and high condition.
(2) Considering the worst test condition, it is tested without any filter capacitors in VBB and VOUT
(3) GND pin network is a 1-kΩ resistor in parallel with a diode BAS21-7-F.
(4) Status II: the function does not perform as designed during the test, but returns automatically to normal operation after the test.
Table 9-5 ISO 16750-2:2010(E) Load Dump Test B in 12-V System(1)(2)(3)(4)(5)
Test Item Test Pulse Severity Level and vs Accordingly Pulse Duration (td) Minimum Number of Pulses or Test Time Burst- Cycle Pulse-Repetition Time Input Resistance (Ω) Function Performance Status Classification
Level Vs/V MIN (s) MAX (s)
Test B 35 40 to 400 ms 5 pulses 60 e 0.5 to 4 Status II
(1) Tested both under input low condition and high condition (DIAG_EN, EN, and VBB are all classified as inputs).
(2) Considering the worst test condition, the device is tested without any filter capacitors on VBB and VOUT.
(3) The GND pin network is a 1-kΩ resistor in parallel with a diode BAS21-7-F.
(4) Status II: the function does not perform as designed during the test, but returns automatically to normal operation after the test.
(5) Select a 39-V external suppressor.