SLVSFI1A July   2021  – December 2021 TPS1HC100-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Accurate Current Sense
      2. 8.3.2 Programmable Current Limit
        1. 8.3.2.1 Capacitive Charging
      3. 8.3.3 Inductive-Load Switching-Off Clamp
      4. 8.3.4 Full Protections and Diagnostics
        1. 8.3.4.1  Short-Circuit and Overload Protection
        2. 8.3.4.2  Open-Load and Short-to-Battery Detection
        3. 8.3.4.3  Short-to-Battery Detection
        4. 8.3.4.4  Reverse-Polarity and Battery Protection
        5. 8.3.4.5  Latch-Off Mode
        6. 8.3.4.6  Thermal Protection Behavior
        7. 8.3.4.7  UVLO Protection
        8. 8.3.4.8  Loss of GND Protection
        9. 8.3.4.9  Loss of Power Supply Protection
        10. 8.3.4.10 Reverse Current Protection
        11. 8.3.4.11 Protection for MCU I/Os
      5. 8.3.5 Diagnostic Enable Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Dynamically Changing Current Limit
        2. 9.2.2.2 AEC Q100-012 Test Grade A Certification
        3. 9.2.2.3 EMC Transient Disturbances Test
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Without a GND Network
      2. 11.2.2 With a GND Network
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4.1 Short-Circuit and Overload Protection

TPS1HC100-Q1 provides output short-circuit protection to ensure that the device prevents current flow in the event of a low impedance path to GND, removing the risk of damage or significant supply droop. The device is ensured to protect against short-circuit events regardless of the state of the ILIM pins and with up to 28-V supply at 125°C.

Figure 8-10 shows the behavior of the TPS1HC100-Q1 when the device is enabled into a short-circuit.

Figure 8-10 Enable into Short-Circuit Behavior (LATCH = 0)

Due to the low impedance path, the output current rapidly increases until it hits the current limit threshold. Due to the response time of the current limiting circuit, the measured maximum current can temporarily exceed the ICL value defined as ICL_ENPS, however, it settles to the current limit regulation value. The amount of deglitch timing between when the overload is recognized and when the system begins to react on it is about 2.5 μs.

In this state, high power is dissipated in the FET, so eventually the internal thermal protection temperature for the FET is reached and the device safely shuts down. Then, if LATCH pin is low, the part waits tRETRY amount of time and turn back on, unless a TABS fault was triggered in which case it can AND the tRETRY timer and the THYS temperature reduction.

Figure 8-11 shows the behavior of the TPS1HC100-Q1 when a short-circuit occurs when the device is in the on-state and already outputting current. When the internal pass FET is fully enabled, the current clamping settling time is slower so to ensure overshoot is limit. The device implements a fast-trip level at a level IOVCR. When this fast-trip threshold is hit, the device immediately shuts off for a short period of time before quickly re-enabling and clamping the current to ICL level after a brief transient overshoot to the higher peak current (ICL_ENPS) level. The device then keeps the current clamped at the regulation current limit until the thermal shutdown temperature is hit and the device safely shuts off.

Figure 8-11 On-State Short-Circuit Behavior

Overload Behavior shows the behavior of the TPS1HC100-Q1 when there is a small change in impedance that sends the load current above the ICL threshold. The current rises (commonly referred to as current creep) to ICL_LINPK above the regulation level. Then the current limit regulation loop kicks in and the current drops to the ICL value.

Figure 8-12 Overload Behavior (Current Creep)

In all of these cases, the internal thermal shutdown is safe to hit repetitively. There is no device risk or lifetime reliability concerns from repeatedly hitting this thermal shutdown level.