SLVSGZ7B
May 2023 – October 2023
TPS2000E
,
TPS2001E
,
TPS2068E
,
TPS2069E
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
13
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Undervoltage Lockout
7.3.2
Enable
7.3.3
Internal Charge Pump
7.3.4
Current Limit
7.3.5
FLT
7.3.6
Output Discharge
7.4
Device Functional Modes
7.4.1
Shutdown Mode
7.4.2
Active Mode
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Input and Output Capacitance
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DGN|8
MPDS046G
DBV|5
MPDS018T
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvsgz7b_oa
slvsgz7b_pm
8.4.1
Layout Guidelines
Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low inductance trace.
Place at least 10-µF low ESR ceramic capacitor near the OUT and GND pins, and make the connections using a low inductance trace.
The PowerPAD must be directly connected to PCB ground plane using wide and short copper trace.