SLVSAY8D June 2011 – January 2016 TPS22920
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Switching Characteristics: VIN = 3.6 V
- 7.7 Switching Characteristics: VIN = 0.9 V
- 7.8 Typical DC Characteristics
- 7.9 TPS22920 Typical AC Characteristics
- 7.10 TPS22920L Typical AC Characteristics
- 8 Parametric Measurement Information
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
- YZP|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Input Capacitor
To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a discharged load capacitor or short-circuit, a capacitor needs to be placed between VIN and GND. A 1-μF ceramic capacitor, CIN, placed close to the pins is usually sufficient. Higher values of CIN can be used to further reduce the voltage drop.
10.1.2 Output Capacitor
A CIN greater than CL is highly recommended due to the integral body diode in the NMOS switch. A CL greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN dip caused by inrush currents during startup.
10.2 Typical Application
Figure 43. Typical Application Circuit
10.2.1 Design Requirements
| DESIGN PARAMETER | EXAMPLE VALUE |
|---|---|
| VIN | 3.3 V |
| CL | 4.7 µF |
| Maximum Acceptable Inrush Current | 40 mA |
10.2.2 Detailed Design Procedure
10.2.2.1 VIN to VOUT Voltage Drop
The VIN to VOUT voltage drop in the device is determined by the RON of the device and the load current. The RON of the device depends upon the VIN condition of the device. Refer to the RON specification of the device in the Electrical Characteristics table of this datasheet. Once the RON of the device is determined based upon the VIN conditions, use Equation 1 to calculate the VIN to VOUT voltage drop:
where
- ΔV = Voltage drop from VIN to VOUT
- ILOAD = Load current
- RON = On-resistance of the device for a specific VIN
- An appropriate ILOAD must be chosen such that the IMAX specification of the device is not violated.
10.2.2.2 Managing Inrush Current
The output capacitors must be charged up from 0-V to VIN when the switch is enabled. This charge arrives in the form of inrush current. Inrush current may be calculated using the following equation:
where
- C = Output capacitance
-
The TPS22920x offers a very slow controlled rise time for minimizing inrush current. This device can be selected based upon the maximum acceptable slew rate which can be calculated using the design requirements and the inrush current equation. An output capacitance of 4.7 μF will be used since the amount of inrush increases with output capacitance:
A device with a slew rate less than 8.5 V/ms must be used to ensure an inrush current of less than 40 mA.
The TPS22920 has a typical rise time of 880 μs at 3.3 V. This results in a slew rate of 3.75 V/ms which meets the Design Requirements.
10.2.3 Application Curves
