SLVSCP7B November   2014  – March 2016 TPS22968-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics (VBIAS = 5 V)
    6. 7.6 Electrical Characteristics (VBIAS = 3.3 V)
    7. 7.7 Electrical Characteristics (VBIAS = 2.5 V)
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
      1. 7.9.1 DC Characteristics
      2. 7.9.2 AC Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 ON and OFF Control
      2. 9.3.2 Quick Output Discharge (QOD) (TPS22968-Q1 Only)
      3. 9.3.3 Adjustable Rise Time
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input Capacitor (Optional)
      2. 10.1.2 Output Capacitor (Optional)
      3. 10.1.3 VIN and VBIAS Voltage Range
        1. 10.1.3.1 Parallel Configuration
        2. 10.1.3.2 Standby Power Reduction
        3. 10.1.3.3 Power Supply Sequencing Without a GPIO Input
        4. 10.1.3.4 Reverse Current Blocking
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inrush Current
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Developmental Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The device is a 5.5 V, 4-A, dual-channel ultra-low RON load switch with controlled turn on. The device contains two N-channel MOSFETs. Each channel can support a maximum continuous current of 4-A. Each channel is controlled by an on/off GPIO-compatible input. The ON pin must be connected and cannot be left floating. The device is designed to control the turn-on rate and therefore the inrush current. By controlling the inrush current, power supply sag can be reduced during turn-on. The slew rate for each channel is set by connecting a capacitor to GND on the CT pins.

The slew rate is proportional to the capacitor on the CT pin. Refer to Adjustable Rise Time to determine the correct CT value for a desired rise time.

The internal circuitry is powered by the VBIAS pin, which supports voltages from 2.5 to 5.5 V. This circuitry includes the charge pump, QOD (TPS22968-Q1 only), and control logic. For these internal blocks to function correctly, a voltage between 2.5 and 5.5 V must be supplied to VBIAS.

When a voltage is supplied to VBIAS and the ON1, 2 pin goes low, the QOD turns on. This connects VOUT1, 2 to GND through an on-chip resistor. The typical pulldown resistance (RPD) is 270 Ω. Note that QOD is not applicable to TPS22968N-Q1.

9.2 Functional Block Diagram

TPS22968-Q1 FBD_SLVSCP7.gif

9.3 Feature Description

9.3.1 ON and OFF Control

The ON pins control the state of the switch. Asserting ON high enables the switch. ON is active high and has a low threshold, making it capable of interfacing with low-voltage signals. The ON pin is compatible with standard GPIO logic threshold. It can be used with any microcontroller with 1.2 V or higher GPIO voltage. This pin cannot be left floating and must be tied either high or low for proper functionality.

9.3.2 Quick Output Discharge (QOD) (TPS22968-Q1 Only)

The TPS22968-Q1 includes a QOD feature. When the switch is disabled, a discharge resistor is connected between VOUT and GND. This resistor has a typical value of 270 Ω and prevents the output from floating while the switch is disabled.

9.3.3 Adjustable Rise Time

A capacitor to GND on the CT pins sets the slew rate for each channel. The capacitor to GND on the CT pins should be rated for 25 V and above. An approximate formula for the relationship between CT and slew rate with VBIAS = 5 V is shown in Equation 1:

Equation 1. SR = 0.35 × CT + 25

where

  • SR = slew rate (in µs/V)
  • CT = the capacitance value on the CT pin (in pF)
  • The units for the constant 25 is in µs/V.

Rise time can be calculated by multiplying the input voltage by the slew rate. Table 1 contains rise time values measured on a typical device.

Table 1. Rise Time Table

CTx (pF) Rise Time (µs) (1) (2)
VIN = 5 V VIN = 3.3 V VIN = 2.5 V VIN = 1.8 V VIN = 1.2 V VIN = 0.8 V
0 84 63 52 43 35 27
220 418 285 223 168 122 88
470 711 479 372 276 196 139
1000 1405 952 738 545 385 271
2200 3236 2174 1684 1246 876 615
4700 6415 4306 3317 2454 1725 1217
10000 13872 9261 7150 5253 3694 2591
(1) 10% - 90%, CL = 0.1 µF, CIN = 1 µF, RL = 10 Ω, VBIAS = 5 V
(2) Typical values at 25°C with a 25-V X7R 10% ceramic capacitor on CT

9.4 Device Functional Modes

Table 2 lists the device function table

Table 2. Functional Table

ONx VINx to VOUTx VOUTx to GND
L Off On
H On Off