SLVSCP7B November   2014  – March 2016 TPS22968-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics (VBIAS = 5 V)
    6. 7.6 Electrical Characteristics (VBIAS = 3.3 V)
    7. 7.7 Electrical Characteristics (VBIAS = 2.5 V)
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
      1. 7.9.1 DC Characteristics
      2. 7.9.2 AC Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 ON and OFF Control
      2. 9.3.2 Quick Output Discharge (QOD) (TPS22968-Q1 Only)
      3. 9.3.3 Adjustable Rise Time
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input Capacitor (Optional)
      2. 10.1.2 Output Capacitor (Optional)
      3. 10.1.3 VIN and VBIAS Voltage Range
        1. 10.1.3.1 Parallel Configuration
        2. 10.1.3.2 Standby Power Reduction
        3. 10.1.3.3 Power Supply Sequencing Without a GPIO Input
        4. 10.1.3.4 Reverse Current Blocking
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inrush Current
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Developmental Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

  • VIN and VOUT traces should be as short and wide as possible to accommodate for high current.
  • Use vias under the exposed thermal pad for thermal relief for high current operation.
  • VINx pins should be bypassed to ground with low-ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 1-µF ceramic with X5R or X7R dielectric. This capacitor should be placed as close to the device pins as possible.
  • VOUTx pins should be bypassed to ground with low-ESR ceramic bypass capacitors. The typical recommended bypass capacitance is one-tenth of the VINx bypass capacitor of X5R or X7R dielectric rating. This capacitor should be placed as close to the device pins as possible.
  • The VBIAS pin should be bypassed to ground with low-ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 0.1-µF ceramic with X5R or X7R dielectric.
  • The CTx capacitors should be placed as close to the device pins as possible. The typical recommended CTx capacitance is a capacitor of X5R or X7R dielectric rating with a rating of 25 V or higher.

12.2 Layout Example

TPS22968-Q1 layout_LVSCP7.gif Figure 43. Layout Schematic

12.3 Thermal Considerations

The maximum IC junction temperature should be restricted to 150°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) for a given ambient temperature, use Equation 5.

Equation 5. TPS22968-Q1 eq_thrm_slvsci4.gif

where

  • PD(max) = maximum allowable power dissipation
  • TJ(max) = maximum allowable junction temperature (150°C for the TPS22968x-Q1)
  • TA = ambient temperature of the device
  • RθJA = junction to air thermal impedance. See Thermal Information. This parameter is highly dependent upon board layout.

Following are two examples demonstrating how to use the above information: For VBIAS = 5 V, VIN = 5 V, the maximum allowable ambient temperature with a 3-A load through each channel can be determined by using the following calculations.

NOTE

When calculating power dissipation in the switch, it is important to use the correct RON value. RON is dependent on the junction temperature of the device.
Equation 6. PD = I2 × R × 2 (multiplied by 2 because there are two channels)
Equation 7. TPS22968-Q1 temp_eq1b_lvscg3.gif
Equation 8. TA = TJ(MAX) – RθJA × 2 × I2 × R
Equation 9. TA = 150°C – 55.6°C/W × 2 × (3 A)2 × 45 mΩ = 105°C

For VBIAS = 5 V, VIN = 5 V, the maximum continuous current for an ambient temperature of 85°C with the same current flowing through each channel can be determined by using the following calculation:

Equation 10. TPS22968-Q1 temp_eq2a_lvscg3.gif
Equation 11. TPS22968-Q1 temp_eq2b_lvscg3.gif
Equation 12. TPS22968-Q1 eq_I_LVSCP7.gif