9.3.1 Operating Frequency

The TPS22994 is designed to be compatible with fast-mode plus and operate up to 1 MHz clock frequency for bus communication. The device is also compatible with standard-mode (100 kHz) and fast-mode (400 kHz). This device can reside on the same bus as high-speed mode (3.4MHz) devices, but the device is not designed to for I²C commands for frequencies greater than 1 MHz. See table below for characteristics of the fast-mode plus, fast-mode, and standard-mode bus speeds.

9.3.2 SDA/SCL Pin Configuration

The SDA and SCL pins of the device operate use an open-drain configuration, and therefore, need pull up resistors to communicate on the I²C bus. The graph below shows recommended values for max pull-up resistors (R_P) and bus capacitances (C_b) to ensure proper bus communications. The SDA and SCL pins should be pulled up to VDD through an appropriately sized R_P based on the graphs below.

9.3.3 Address (ADDx) Pin Configuration

The TPS22994 can be configured with an unique I²C slave addresses by using the ADDx pins. There are 3 ADDx pins that can be tied high to VDD or low to GND (independent of each other) to get up to 7 different slave addresses. The ADDx pins should be tied to GND if the I²C functionality of the device is not to be used. External pull-up resistors for the ADDx are optional as the ADDx inputs are high impedance. The following table shows the ADDx pin tie-offs with their associated slave addresses (assuming an eight bit word, where the LSB is the read/write bit and the device address bits are the 7 MSB bits) :

9.3.4 On-Delay Control

Using the I²C interface, the configuration register for each channel can be set for different ON delays for power sequencing. The typical options for delay are as follows (see Switching Characteristics, VBIAS = 7.2 V table):

00 = 11 µs delay (default register value)
01 = 105 µs delay
10 = 330 µs delay
11 = 950 µs delay

It is not recommended to change the delay value for the duration of the delay that is programmed when the channel is enabled (except for ON-delay setting of '00' which requires a minimum of 100µs wait time before changing the setting). This could result in erratic behavior where the output could toggle unintentionally but would eventually recover by the end of the delay time programmed at the time of channel enable.

9.3.5 Slew Rate Control

Using the I²C interface, the configuration register for each channel can be set for different slew rates for inrush current control and power sequencing. The typical options for slew rate are as follows (see Switching Characteristics table for VOUTx rise times):

000 = 1 µs/V
001 = 150 µs/V
010 = 250 µs/V
011 = 460 µs/V (default register value)
100 = 890 µs/V
101 = invalid slew rate
110 = invalid slew rate
111 = reserved

9.3.6 Quick Output Discharge (QOD) Control

Using the I²C interface, the configuration register for each channel can be set for different output discharge resistors. The typical options for QOD are as follows (see Electrical Characteristics table):

00 = 110 Ω
01 = 490 Ω
10 = 951 Ω (default register value)
11 = No QOD (high impedance)

9.3.7 Mode Registers

Using the I²C interface, the mode registers can be programmed to the desired on/off status for each channel. The contents of these registers are copied over to the control registers when a SwitchALL™ command is issued, allowing all channels of the device to transition to their desired output states synchronously. See the I²C Protocol section and the Application Scenario section for more information on how to use the mode registers in conjunction with the SwitchALL^TM command.

9.3.8 SwitchALL™ Command

I²C controlled channels can respond to a common slave address. This feature allows multiple load switches on the same I²C bus to respond simultaneously. The SwitchALL™ address is EEh. During a SwitchALL™ command, the lower four bits (bits 0 through 3) of the mode register is copied to the lower four bits (bits 0 through 3) of the control register. The mode register to be invoked is referenced in the body of the SwitchALL™ command. The structure of the SwitchALL™ command is as follows (as shown in Figure 43): <start><SwitchALL™ addr><mode addr><stop>. See the I²C Protocol section and the Application Scenario section for more information on how to use the SwitchALL^TM command in conjunction with the mode registers.

Figure 43. Composition of SwitchALL™ Command

9.3.9 V_DD Supply For I²C Operation

The SDA and SCL pins of the device must be pulled up to the VDD voltage of the device for proper I²C bus communication. See Recommended Operating Conditions for VDD operating range.

9.3.10 Input Capacitor (Optional)

To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a discharged load capacitor or short-circuit, a capacitor needs to be placed between V_IN and GND. A 1-µF ceramic capacitor, C_IN, placed close to the pins, is usually sufficient. Higher values of C_IN can be used to further reduce the voltage drop during high-current application. When switching heavy loads, it is recommended to have an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop. For the fastest slew rate setting of the device, a CIN to CL ratio of at least 100 to 1 is recommended to avoid excessive voltage drop.

9.3.11 Output Capacitor (Optional)

Due to the integrated body diode of the NMOS switch, a C_IN greater than C_L is highly recommended. A C_L greater than C_IN can cause V_OUT to exceed V_IN when the system supply is removed. This could result in current flow through the body diode from V_OUT to V_IN. A C_IN to C_L ratio of at least 10 to 1 is recommended for minimizing V_IN dip caused by inrush currents during startup. For the fastest slew rate setting of the device, a CIN to CL ratio of at least 100 to 1 is recommended to minimize V_IN dip caused by inrush currents during startup.

9.3.12 I²C Protocol

The following section will cover the standard I²C protocol used in the TPS22994. In the I²C protocol, the following basic blocks are present in every command (except for the SwitchALL^TM command):

• Start/stop bit – marks the beginning and end of each command.
• Slave address – the unique address of the slave device.
• Sub address – this includes the register address and the auto-increment bit.
• Data byte – data being written to the register. Eight bits must always be transferred even if a single bit is being written or read.
• Auto-increment bit – setting this bit to ‘1’ turns on the auto-increment functionality; setting this bit to ‘0’ turns off the auto-increment functionality.
• Write/read bit – this bit signifies if the command being sent will result in reading from a register or writing to a register. Setting this bit to ‘0’ signifies a write, and setting this bit to ‘1’ signifies a read.
• Acknowledge bit – this bit signifies if the master or slave has received the preceding data byte.

9.3.12.3 Write Command

During the write command, the write/read bit is set to ‘0’, signifying that the register in question will be written to. Figure 44 the composition of the write protocol to a single register:

Figure 44. Data Write to a Single Register

Number of clock cycles for single register write: 29

If multiple consecutive registers must be written to, a short-hand version of the write command can be used. Using the auto-increment functionality of I²C, the device will increment the register address after each byte. Figure 45 shows the composition of the write protocol to multiple consecutive registers:

Figure 45. Data Write to Consecutive Registers

Number of clock cycles for consecutive register write: 20 + (Number of registers) x 9

The write command is always ended with a STOP bit after the desired registers have been written to. If multiple non-consecutive registers must be written to, then the format in Figure 44 must be followed.

9.3.12.4 Read Command

During the read command, the write/read bit is set to ‘1’, signifying that the register in question will be read from. However, a read protocol includes a “dummy” write sequence to ensure that the memory pointer in the device is pointing to the correct register that will be read. Failure to precede the read command with a write command may result in a read from a random register. Figure 46 shows the composition of the read protocol to a single register:

Figure 46. Data Read to a Single Register

Number of clock cycles for single register read: 39

If multiple registers must be read from, a short-hand version of the read command can be used. Using the auto-increment functionality of I²C, the device will increment the register address after each byte. Figure 47 shows the composition of the read protocol to multiple consecutive registers:

Figure 47. Data Read to Consecutive Registers

Number of clock cycles for consecutive register write: 30 + (Number of registers) x 9

The read command is always ended with a STOP bit after the desired registers have been read from. If multiple non-consecutive registers must be read from, then the format in Figure 46 must be followed.

9.3.12.5 SwitchALL^TM Command

The SwitchALL^TM command allows multiple devices in the same I²C bus to respond synchronously to the same command from the master. Every TPS22994 device has a shared address which allows for multiple devices to respond or execute a pre-determined action with a single command. Figure 48 shows the composition of the SwitchALL^TM command:

Figure 48. SwitchALL^TM Command Structure

Number of clock cycles for a SwitchALL^TM command: 20

9.4.1 I²C Control

When power is applied to VBIAS, the device comes up in its default mode of GPIO operation where the channel outputs can be controlled solely via the ON pins. At any time, if SDA and SCL are present and valid, the device can be configured to be controlled via I²C (if in GPIO control) or GPIO (if in I²C control).

The control register (address 05h) can be configured for GPIO or I²C enable on a per channel basis.

9.4.2 GPIO Control

There are four ON pins to enable/disable the four channels. Each ON pin controls the state of the switch by default upon power up. Asserting ON high enables the switch. ON is active high and has a low threshold, making it capable of interfacing with low-voltage signals. The ON pin is compatible with standard GPIO logic threshold. It can be used with any microcontroller with 1.2 V or higher voltage GPIO.