SLVSCL4B August   2014  – September 2014 TPS22994

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Recommended Operating Conditions
    2. 8.2 Absolute Maximum Ratings
    3. 8.3 Handling Ratings
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics, VBIAS = 7.2 V
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Operating Frequency
      2. 9.3.2  SDA/SCL Pin Configuration
      3. 9.3.3  Address (ADDx) Pin Configuration
      4. 9.3.4  On-Delay Control
      5. 9.3.5  Slew Rate Control
      6. 9.3.6  Quick Output Discharge (QOD) Control
      7. 9.3.7  Mode Registers
      8. 9.3.8  SwitchALL™ Command
      9. 9.3.9  VDD Supply For I2C Operation
      10. 9.3.10 Input Capacitor (Optional)
      11. 9.3.11 Output Capacitor (Optional)
      12. 9.3.12 I2C Protocol
        1. 9.3.12.1 Start and Stop Bit
        2. 9.3.12.2 Auto-increment Bit
        3. 9.3.12.3 Write Command
        4. 9.3.12.4 Read Command
        5. 9.3.12.5 SwitchALLTM Command
    4. 9.4 Device Functional Modes
      1. 9.4.1 I2C Control
      2. 9.4.2 GPIO Control
    5. 9.5 Register Map
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input Capacitor (Optional)
      2. 10.1.2 Output Capacitor (Optional)
      3. 10.1.3 Switch from GPIO Control to I2C Control (and vice versa)
      4. 10.1.4 Configuration of Configuration Registers
        1. 10.1.4.1 Single Register Configuration
        2. 10.1.4.2 Multi-register Configuration (Consecutive Registers)
      5. 10.1.5 Configuration of Mode Registers
      6. 10.1.6 Turn-on/Turn-off of Channels
    2. 10.2 Typical Application
      1. 10.2.1 Tying Multiple Channels in Parallel
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Cold Boot Programming of All Registers
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Power Sequencing Without I2C
        1. 10.2.3.1 Design Requirements
          1. 10.2.3.1.1 Reading From the Registers
        2. 10.2.3.2 Detailed Design Procedure
          1. 10.2.3.2.1 VIN to VOUT Voltage Drop
          2. 10.2.3.2.2 Inrush Current
        3. 10.2.3.3 Application Curves
  11. 11Layout
    1. 11.1 Board Layout
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Specifications

8.1 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VINx Input voltage for VIN1, VIN2, VIN3, VIN4 For VBIAS < 4.6 V 1.0 (VBIAS – 1 V) V
For VBIAS ≥ 4.6 V 1.0 3.6
VBIAS Supply voltage for VBIAS 2.7 17.2 V
VDD Supply voltage for VDD 1.62 3.6 V
VADDx Input voltage for ADD1, ADD2, ADD3 0 VDD V
VONx Input voltage for ON1, ON2, ON3, ON4 0 5 V
VOUTx Output voltage for VOUT1, VOUT2, VOUT3, VOUT4 0 VINx V
CINx Input capacitor on VIN1, VIN2, VIN3, VIN4 1(1) µF
(1) Refer to application section.

8.2 Absolute Maximum Ratings(1)

Over operating free-air temperature range (unless otherwise noted)
VALUE UNIT(2)
MIN MAX
VINx Input voltage for VIN1, VIN2, VIN3, VIN4 –0.3 4 V
VBIAS Supply voltage for VBIAS –0.3 20 V
VOUTx Output voltage for VOUT1, VOUT2, VOUT3, VOUT4 –0.3 4 V
VDD, VSCL,
VSDA, VADDx		 Input voltage for VDD, SCL, SDA, ADD1, ADD2, ADD3 –0.3 4 V
VONx Input voltage for ON1, ON2, ON3, ON4 –0.3 6 V
IMAX Maximum continuous switch current per channel 1 A
TA Operating free-air temperature(3) –40 85 °C
TJ Maximum junction temperature 125 °C
TLEAD Maximum lead temperature (10-s soldering time) 300 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max))

8.3 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature –65 150 °C
ESD(1) Electrostatic discharge protection Human-Body Model (HBM)(2) –2000 2000 V
Charged-Device Model (CDM)(3) –-500 500 V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

8.4 Thermal Information

THERMAL METRIC(1)(2) TPS22994 UNIT
RUK
20 PINS
ΘJA Junction-to-ambient thermal resistance 46 °C/W
ΘJC(top) Junction-to-case(top) thermal resistance 50
ΘJB Junction-to-board thermal resistance 18
ΨJT Junction-to-top characterization parameter 0.7
ΨJB Junction-to-board characterization parameter 18
ΘJC(bottom) Junction-to-case(bottom) thermal resistance 4.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

8.5 Electrical Characteristics

The specification applies over the operating ambient temperature –40°C ≤ TA ≤ 85°C (Full) (unless otherwise noted). Typical values are for TA = 25°C. VBIAS = 7.2 V (unless otherwise noted).
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
POWER SUPPLIES CURRENTS AND LEAKAGES
IQ, VBIAS Quiescent current for VBIAS (all four channels) IOUT1,2,3,4 = 0 A,
VIN1,2,3,4 = lower of (VBIAS-1 V) or 3.6 V,
VON1,2,3,4 = 3.6 V,
VDD = 0 V		 VBIAS = 2.7 V Full 18.3 27.6 µA
VBIAS = 3.3 V 18.9 28.6
VBIAS = 4.5 V 19.4 29.9
VBIAS = 5.2 V 19.9 30.3
VBIAS = 7.2 V 21.1 33.6
VBIAS = 10.8 V 21.2 34.8
VBIAS = 12.6 V 21.2 35.0
VBIAS = 17.2 V 21.2 35.7
Quiescent current for VBIAS (single channel) IOUT1,2,3,4 = 0 A,
VIN1 = lower of (VBIAS-1 V) or 3.6 V,
VON1 = 3.6 V,
VIN2,3,4 = VON2,3,4 = 0 V,
VDD = 0 V		 VBIAS = 2.7 V Full 8.3 16.6 µA
VBIAS = 3.3 V 8.8 17.6
VBIAS = 4.5 V 9.5 18.9
VBIAS = 5.2 V 9.9 19.6
VBIAS = 7.2 V 11.3 22.5
VBIAS = 10.8 V 11.7 23.6
VBIAS = 12.6 V 11.7 23.8
VBIAS = 17.2 V 11.9 24.4
IQ, VDD Quiescent current for VDD IOUT1,2,3,4 = 0 A,
VIN1,2,3,4 = VON1,2,3,4 = 3.6 V,
fSCL = 0 Hz		 VDD = 1.8 V Full 0.6 1.1 µA
VDD = 3.6 V 1.2 1.9
IDYN, VDD Average dynamic current for VDD during I2C communication IOUT1,2,3,4 = 0 A,
VIN1,2,3,4 = VON1,2,3,4 = 3.6 V,
fSCL = 1 MHz		 VDD = 1.8 V Full 7.7 µA
VDD = 3.6 V 19.0
IDYN, VBIAS Average dynamic current for VBIAS (all four channels) during I2C communication IOUT1,2,3,4 = 0 A,
VIN1,2,3,4 = lower of (VBIAS-1 V) or 3.6 V,
VON1,2,3,4 = 3.6 V,
fSCL=1 MHz		 VBIAS = 3.3 V Full 65.0 µA
VBIAS = 5.2 V 66.9
VBIAS = 7.2 V 68.4
VBIAS = 10.8 V 68.5
VBIAS = 12.6 V 68.6
VBIAS = 17.2 V 69.1
Average dynamic current for VBIAS (single channel) during I2C communication IOUT1,2,3,4 = 0 A,
VIN1,2,3,4 = lower of (VBIAS-1 V) or 3.6 V,
VON1,2,3,4 = 3.6 V,
VIN2,3,4 = VON2,3,4 = 0 V,
fSCL= 1 MHz		 VBIAS = 3.3 V Full 48.0 µA
VBIAS = 5.2 V 58.2
VBIAS = 7.2 V 58.9
VBIAS = 10.8 V 60.2
VBIAS = 12.6 V 60.2
VBIAS = 17.2 V 60.7
ISD, VBIAS Shutdown current for VBIAS (all four channels) VON1,2,3,4 = 0 V, VOUT1,2,3,4 = 0 V, VDD = 3.6 V,
VBIAS = 17.2V		 Full 6.5 12.8 µA
ISD, VDD Shutdown current for VDD VON1,2,3,4 = 0 V, VOUT1,2,3,4 = 0 V,
VDD = 3.6 V		 Full 1.2 1.9 µA
ISD, VINx Shutdown current for VINx VONx = 0 V, VOUTx = 0 V, VDD = 3.6 V VINx = 3.6 V Full 0.005 1.0 µA
VINx = 3.3 V 0.004 1.0
VINx = 1.8 V 0.003 0.5
VINx = 1.5 V 0.003 0.5
VINx = 1.0 V 0.003 0.5
IONx Leakage current for ONx VONx = 5 V Full 0.003 0.1 µA
IADDx Leakage current for ADDx VADDx = 3.6 V Full 0.002 0.2 µA
ISCL Leakage current for SCL VSCL = 3.6 V Full 0.002 0.2 µA
ISDA Leakage current for SDA VSDA = 3.6 V Full 0.002 0.2 µA
RESISTANCE CHARACTERISTICS
RON On-state resistance VBIAS = 7.2 V, IOUT = –200 mA VIN = 3.3 V 25°C 40.6 50.3 mΩ
Full 58.5
VIN = 2.5 V 25°C 40.5 50.2 mΩ
Full 58.5
VIN = 1.8 V 25°C 40.5 50.1 mΩ
Full 58.5
VIN = 1.5 V 25°C 40.5 50.1 mΩ
Full 58.5
VIN = 1.0 V 25°C 40.5 49.9 mΩ
Full 58.5
VBIAS = 5.2 V, IOUT = –200 mA VIN = 3.3 V 25°C 60.4 64.0 mΩ
Full 71.0
VIN = 2.5 V 25°C 44.7 53.1 mΩ
Full 65.2
VIN = 1.8 V 25°C 41.5 50.3 mΩ
Full 60.9
VIN = 1.5 V 25°C 40.8 50.3 mΩ
Full 60.5
VIN = 1.0 V 25°C 40.6 50.1 mΩ
Full 60.3
VBIAS = 3.3 V, IOUT = –200 mA VIN = 2.3 V 25°C 114.2 166.0 mΩ
Full 175.0
VIN = 1.8 V 25°C 64.2 85.9 mΩ
Full 94.4
VIN = 1.5 V 25°C 55.4 69.5 mΩ
Full 81.0
VIN = 1.0 V 25°C 48.0 57.9 mΩ
Full 70.0
RPD Output pulldown resistance VIN = 3.3 V, VON = 0 V, IOUT = 1 mA, QOD[1:0] = 00 25°C 93 Ω
VIN = 3.3 V, VON = 0 V, IOUT = 1 mA, QOD[1:0] = 01 25°C 470
VIN = 3.3 V, VON = 0 V, IOUT = 1 mA, QOD[1:0] = 10 25°C 940
VIN = 3.3 V, VON = 0 V, IOUT = 1 mA, QOD[1:0] = 11 No QOD
THRESHOLD CHARACTERISTICS
VIH, ADDx High-level input voltage for ADDx Full 0.7 × VDD V
VIL, ADDx Low-level input voltage for ADDx Full 0.3×VDD V
VIH, ONx High-level input voltage for ONx Full 1.05 5 V
VIL, ONx Low-level input voltage for ONx Full 0 0.4 V
VHYS, ONx Hysteresis for ONx VBIAS = 2.7 V 25°C 107 mV
VBIAS = 5.2 V 105
VBIAS = 7.2 V 107
VBIAS = 10.8 V 108
VBIAS = 12.6 V 109
VBIAS = 17.2 V 108
I2C CHARACTERISTICS
fSCL(1) Clock frequency Full 1 MHz
tSU, SDA(1) Setup time for SDA fSCL = 1 MHz (fast mode plus) Full 50 ns
tHD, SDA(1) Hold time for SDA Full 0 ns
IOL, SDA SDA output low current VOL,SDA = 0.4 V 25°C 8 mA
VIH, SDA High-level input voltage for SDA Full 0.7 × VDD VDD V
VIH, SCL High-level input voltage for SCL Full 0.7 × VDD VDD V
VIL, SDA Low-level input voltage for SDA Full 0 0.3×VDD V
VIL, SCL Low-level input voltage for SCL Full 0 0.3×VDD V
(1) Parameter verified by design.

8.6 Switching Characteristics, VBIAS = 7.2 V

Values below are typical values at TA = 25°C. VBIAS = 7.2V (unless otherwise noted).
PARAMETER TEST CONDITION VIN VOLTAGE UNIT
3.3 V 1.8 V 1.5 V 1.0 V
tON VOUTx turn-on time VBIAS = 7.2 V,
RL= 10 Ω, CL= 0.1 µF,
QOD[1:0] = 10,
ON-delay[6:5] = 00		 Slew rate[4:2] = 000 10.2 10.0 9.9 9.9 µs
Slew rate[4:2] = 001 220 159 147 124
Slew rate[4:2] = 010 380 274 252 213
Slew rate[4:2] = 011 674 486 446 377
Slew rate[4:2] = 100 1334 967 888 749
tOFF VOUTx turn-off time VBIAS = 7.2 V, RL=10 Ω, CL=0.1 µF, QOD[1:0] = 10, ON-delay[6:5] = 00 2.5 2.5 2.5 2.5 µs
tR VOUTx rise time VBIAS = 7.2 V, RL= 10 Ω, CL = 0.1 µF,
QOD[1:0] = 10, ON-delay[6:5] = 00		 Slew rate[4:2] = 000 1.4 0.9 0.8 0.7 µs
Slew rate[4:2] = 001 271 178 158 125
Slew rate[4:2] = 010 471 309 275 218
Slew rate[4:2] = 011 835 549 489 390
Slew rate[4:2] = 100 1674 1096 976 774
tF VOUTx fall time VBIAS = 7.2 V, RL= 10 Ω, CL= 0.1 µF, QOD[1:0] = 10, ON-delay[6:5] = 00 2.3 2.3 2.3 2.3 µs
tD VOUTx ON delay time VBIAS = 7.2 V, RL= 10 Ω, CL= 0.1 µF,
QOD[1:0] = 10, Slew rate[6:5] = 000		 ON delay[4:2] = 00 9.6 9.6 9.6 9.6 µs
ON delay[4:2] = 01 87 87 87 87
ON delay[4:2] = 10 295 295 295 295
ON delay[4:2] = 11 846 846 846 846

Switching Characteristics, VBIAS = 3.3 V

Values below are typical values at TA = 25°C. VBIAS = 3.3 V (unless otherwise noted).
PARAMETER TEST CONDITION VIN VOLTAGE UNIT
1.8V 1.5V 1.0V
tON VOUTx turn-on time VBIAS = 3.3 V,
RL=10 Ω, CL=0.1 µF,
QOD[1:0] = 10,
ON-delay[6:5] = 00		 Slew rate[4:2] = 000 8.4 8.3 8.1 µs
Slew rate[4:2] = 001 165 152 129
Slew rate[4:2] = 010 283 260 221
Slew rate[4:2] = 011 502 460 389
Slew rate[4:2] = 100 997 915 773
tOFF VOUTx turn-off time VBIAS = 3.3 V, RL=10 Ω, CL=0.1 µF, QOD[1:0] = 10, ON-delay[6:5] = 00 2.5 2.6 2.8 µs
tR VOUTx rise time VBIAS = 3.3 V, RL=10 Ω, CL=0.1 µF,
QOD[1:0] = 10, ON-delay[6:5] = 00		 Slew rate[4:2] = 000 2.8 2.4 1.8 µs
Slew rate[4:2] = 001 184 163 128
Slew rate[4:2] = 010 318 283 224
Slew rate[4:2] = 011 565 501 398
Slew rate[4:2] = 100 1126 1002 791
tF VOUTx fall time VBIAS = 3.3 V, RL=10 Ω, CL= 0.1 µF, QOD[1:0] = 10, ON-delay[6:5] = 00 2.2 2.2 2.1 µs
tD VOUTx ON delay time VBIAS = 3.3 V, RL=10 Ω, CL=0.1 µF,
QOD[1:0] = 10, Slew rate[6:5] = 000		 ON delay[4:2] = 00 7.3 7.3 7.3 µs
ON delay[4:2] = 01 89 89 89
ON delay[4:2] = 10 296 296 296
ON delay[4:2] = 11 846 846 846
tst_cir1_slvscl4.gif
A. Rise and fall times of the control signal is 100 ns.
B. All switching measurements are done using GPIO control only.
Figure 1. Test Circuit
tst_cir2_slvscl4.gifFigure 2. tON/tOFF Waveforms

8.7 Typical Characteristics

D001_SLVSCL4.gif
VBIAS = 7.2 V VINx = 3.6 V
Figure 3. IQ,VDD vs. VDD
D003_SLVSCL4.gif
VINx = lower of (VBIAS-1V) or 3.6 V VDD = 3.6 V
Figure 5. IQ,VBIAS vs. VBIAS (all channels)
D005_SLVSCL4.gif
VINx = lower of (VBIAS-1V) or 3.6 V VDD = 3.6 V
Figure 7. ISD,VBIAS vs. VBIAS
D007_SLVSCL4.gif
VBIAS = 7.2 V IOUT = 200 mA
Figure 9. RON vs. VIN
D009_SLVSCL4.gif
TA = 25°C
Figure 11. RON vs. VIN
D012_SLVSCL4.gif
VINx = lower of (VBIAS-1 V) or 3.6 V TA = 25°C
Figure 13. VHYS, ONx vs. VBIAS
D014_SLVSCL4.gif
VBIAS = 7.2 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 000
Figure 15. tR vs. VIN
D016_SLVSCL4.gif
VBIAS = 7.2 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 001
Figure 17. tR vs. VIN
D018_SLVSCL4.gif
VBIAS = 7.2 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 010
Figure 19. tR vs. VIN
D020_SLVSCL4.gif
VBIAS = 7.2 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 011
Figure 21. tR vs. VIN
D022_SLVSCL4.gif
VBIAS = 7.2 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 100
Figure 23. tR vs. VIN
D024_SLVSCL4.gif
ON-delay[6:5] = 00 VDD = 3.6 V RL = 10 Ω
Figure 25. tD vs. VBIAS
D026_SLVSCL4.gif
ON-delay[6:5] = 10 V VDD = 3.6 V RL = 10 Ω
Figure 27. tD vs. VBIAS
D028_SLVSCL4.gif
VBIAS = 7.2 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 000
Figure 29. tON vs. VIN
D030_SLVSCL4.gif
VBIAS = 7.2 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 001
Figure 31. tON vs. VIN
D030_SLVSCL4.gif
A.
VBIAS = 7.2 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 010
Figure 33. tON vs. VIN
D034_SLVSCL4.gif
VBIAS = 7.2 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 011
Figure 35. tON vs. VIN
D036_SLVSCL4.gif
VBIAS = 7.2 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 100
Figure 37. tON vs. VIN
D038_SLVSCL4.gif
VBIAS = 7.2 V VDD = 3.6 V RL = 10 Ω
Figure 39. tF vs. VIN
D040_SLVSCL4.gif
VBIAS = 7.2 V VDD = 3.6 V RL = 10 Ω
Figure 41. tOFF vs. VIN
D002_SLVSCL4.gif
VBIAS = 7.2 V VINx = 3.6 V
Figure 4. ISD,VDD vs. VDD
D004_SLVSCL4.gif
VINx = lower of (VBIAS-1V) or 3.6 V VDD = 3.6 V
Figure 6. IQ,VBIAS vs. VBIAS (single channel)
D006_SLVSCL4.gif
VBIAS = 7.2 V VDD = 3.6 V
Figure 8. ISD,VIN vs. VIN
D008_SLVSCL4.gif
VBIAS = 7.2 V IOUT = 1 A
Figure 10. RON vs. VIN (single channel)
D010_SLVSCL4.gif
VINx = lower of (VBIAS-1 V) or 3.6 V TA = 25°C
Figure 12. VIH/VIL for ONx vs. VBIAS
D013_SLVSCL4.gif
TA = 25°C
Figure 14. RPD vs. VBIAS
D015_SLVSCL4.gif
VBIAS = 3.3 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 000
Figure 16. tR vs. VIN
D017_SLVSCL4.gif
VBIAS = 3.3 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 001
Figure 18. tR vs. VIN
D019_SLVSCL4.gif
VBIAS = 3.3 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 010
Figure 20. tR vs. VIN
D021_SLVSCL4.gif
VBIAS = 3.3 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 011
Figure 22. tR vs. VIN
D023_SLVSCL4.gif
VBIAS = 3.3 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 100
Figure 24. tR vs. VIN
D025_SLVSCL4.gif
ON-delay[6:5] = 01 VDD = 3.6 V RL = 10 Ω
Figure 26. tD vs. VBIAS
D027_SLVSCL4.gif
ON-delay[6:5] = 11 VDD = 3.6 V RL = 10 Ω
Figure 28. tD vs. VBIAS
D029_SLVSCL4.gif
VBIAS = 3.3 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 000
Figure 30. tON vs. VIN
D031_SLVSCL4.gif
VBIAS = 3.3 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 001
Figure 32. tON vs. VIN
D031_SLVSCL4.gif
VBIAS = 3.3 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 010
Figure 34. tON vs. VIN
D035_SLVSCL4.gif
VBIAS = 3.3 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 011
Figure 36. tON vs. VIN
D037_SLVSCL4.gif
VBIAS = 3.3 V VDD = 3.6 V RL = 10 Ω
Slew rate[4:2] = 100
Figure 38. tON vs. VIN
D039_SLVSCL4.gif
VBIAS = 3.3 V VDD = 3.6 V RL = 10 Ω
Figure 40. tF vs. VIN
D041_SLVSCL4.gif
VBIAS = 3.3 V VDD = 3.6 V RL = 10 Ω
Figure 42. tOFF vs. VIN