SLUSCM4B October   2017  – November 2018 TPS2372

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PG Power Good (Converter Enable) Pin Interface
      2. 7.3.2 CLSA and CLSB Classification, AUTCLS
      3. 7.3.3 DEN Detection and Enable
      4. 7.3.4 Internal Pass MOSFET and Inrush Delay Enable, IRSHDL_EN
      5. 7.3.5 TPH, TPL and BT PSE Type Indicators
      6. 7.3.6 AMPS_CTL, MPS_DUTY and Automatic MPS
      7. 7.3.7 VDD Supply Voltage
      8. 7.3.8 VSS
      9. 7.3.9 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Startup Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Autoclass
      7. 7.4.7  Inrush and Startup
      8. 7.4.8  Maintain Power Signature
      9. 7.4.9  Startup and Converter Operation
      10. 7.4.10 PD Hotswap Operation
      11. 7.4.11 Startup and Power Management, PG and TPH, TPL, BT
      12. 7.4.12 Using DEN to Disable PoE
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistors, RCLSA and RCLSB
        6. 8.2.2.6  Opto-isolators for TPH, TPL and BT
        7. 8.2.2.7  Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
        8. 8.2.2.8  Internal Voltage Reference, RREF
        9. 8.2.2.9  Autoclass
        10. 8.2.2.10 Inrush Delay
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Links
      2. 11.1.2 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6 AMPS_CTL, MPS_DUTY and Automatic MPS

To maintain PSE power, the AMPS_CTL output generates voltage pulses. This is translated into current pulses by connecting a resistor between AMPS_CTL and VSS. These pulses are automatically generated as long as the current through the RTN-to-VSS path is not high enough (< ~28 mA). Typical resistor value of 1.3 kΩ is recommended, in applications where the load current may go below ~20 mA and the PSE power has to be maintained.

If a Type 3 or 4 PSE is detected, the MPS_DUTY input can be used to select one out of three duty-cycles (5.4%, 8.1%, 12.5%). The selection is based on various system parameters, which include the amount of bulk capacitance, the input cable impedance and the type of input bridge. Also, inserting a blocking diode (or MOSFET) between the bulk capacitor and the TPS2372 allows the selection of a shorter MPS duty-cycle.Table 4 should be used to select a proper MPS Duty Cycle.

Table 4. MPS Duty-Cycle Selection

PSE Type MPS_DUTY MPS Duty-Cycle
1,2 - 26%
3,4 Short to VSS 12.5%
3,4 Resistance (60.4K typ.) to VSS 8.1%
3,4 Open 5.4%

Table 5. System Conditions and MPS Duty-Cycle

Expected PoE PD System Conditions MPS_DUTY Selection
CBULK
Blocking Diode 		CBULK Cable Length MPS
Duty-cycle 		Pin Termination IMPS (mA)
Yes Any 0 -100m 5.4% or longer Open 18.5
No ≤ 60 µF 8.1% or longer 60 kΩ to VSS 18.5
No > 60 µF, ≤ 120 µF 12.5% Short to VSS 18.5
No ≤ 120 µF 5.4% or longer(1) Open 18.5
No > 120 µF, ≤ 300 µF 8.1% or longer (1) 60 kΩ to VSS 18.5
(1) Applicable when PSE voltage step-down events are unlikely or are not expected to exceed -0.4 V.