7.3.2 CLSA and CLSB Classification, AUTCLS

Each of the two external resistors (R_CLSA and R_CLSB in Figure 22) connected between the CLSA (first and second class event) and CLSB (third and any subsequent class event) pins and VSS provide a distinct classification signature to the PSE, and are used to define the power class requested by the PD. The controller places a voltage of approximately 2.5 V across CLSA (first or second class event) or CLSB (all additional class events) external resistor whenever the voltage differential between VDD and VSS lies from about 10.9 V to 22 V. The current drawn by each resistor, combined with the internal current drain of the controller and any leakage through the internal pass MOSFET, creates the classification signature current. Table 1 lists the external resistor values required for each of the PD power ranges defined by IEEE802.3bt. The number of classification cycles then determines how much power is allocated by the PSE. The maximum average power drawn by the PD, plus the power supplied to the downstream load, should not exceed the maximum power indicated in Table 1, as well as the maximum power allocated by the PSE based on the number of classification cycles.

Type 2 and Type 3 PSEs may perform two classification cycles if Class 4 signature is presented on the first cycle. Likewise, Type 3 and Type 4 PSEs may perform four classification cycles if Class 4 signature is presented on the first two cycles and Class 0 or 1 signature is presented on the third cycle. Also, Type 4 PSEs may perform five classification cycles if Class 4 signature is presented on the first two cycles and Class 2 or 3 signature is presented on the third cycle.

The AUTCLS input is used to enable the Autoclass function during classification. When enabled, the class signature during the first class event drops to class 0 current level after a time t_ACS of the first class event, indicating to a Type 3 or 4 PSE that it supports Autoclass.