SLVSER6B May   2020  – November 2020 TPS23730

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: DC-DC Controller Section
    6. 7.6 Electrical Characteristics PoE
    7.     14
    8. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CLSA, CLSB Classification
      2. 8.3.2  DEN Detection and Enable
      3. 8.3.3  APD Auxiliary Power Detect
      4. 8.3.4  PPD Power Detect
      5. 8.3.5  Internal Pass MOSFET
      6. 8.3.6  TPH, TPL and BT PSE Type Indicators
      7. 8.3.7  DC-DC Controller Features
        1. 8.3.7.1 VCC, VB, VBG and Advanced PWM Startup
        2.       28
        3. 8.3.7.2 CS, Current Slope Compensation and Blanking
        4. 8.3.7.3 COMP, FB, EA_DIS, CP, PSRS and Opto-less Feedback
        5. 8.3.7.4 FRS Frequency Setting and Synchronization
        6. 8.3.7.5 DTHR and Frequency Dithering for Spread Spectrum Applications
        7. 8.3.7.6 SST and Soft-Start of the Switcher
        8. 8.3.7.7 SST, I_STP, LINEUV and Soft-Stop of the Switcher
      8. 8.3.8  Switching FET Driver - GATE, GTA2, DT
      9. 8.3.9  EMPS and Automatic MPS
      10. 8.3.10 VDD Supply Voltage
      11. 8.3.11 RTN, AGND, GND
      12. 8.3.12 VSS
      13. 8.3.13 Exposed Thermal pads - PAD_G and PAD_S
    4. 8.4 Device Functional Modes
      1. 8.4.1  PoE Overview
      2. 8.4.2  Threshold Voltages
      3. 8.4.3  PoE Start-Up Sequence
      4. 8.4.4  Detection
      5. 8.4.5  Hardware Classification
      6. 8.4.6  Maintain Power Signature (MPS)
      7. 8.4.7  Advanced Start-Up and Converter Operation
      8. 8.4.8  Line Undervoltage Protection and Converter Operation
      9. 8.4.9  PD Self-Protection
      10. 8.4.10 Thermal Shutdown - DC-DC Controller
      11. 8.4.11 Adapter ORing
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1  Input Bridges and Schottky Diodes
          2. 9.2.1.1.2  Input TVS Protection
          3. 9.2.1.1.3  Input Bypass Capacitor
          4. 9.2.1.1.4  Detection Resistor, RDEN
          5. 9.2.1.1.5  Classification Resistor, RCLSA and RCLSB.
          6. 9.2.1.1.6  Dead Time Resistor, RDT
          7. 9.2.1.1.7  APD Pin Divider Network, RAPD1, RAPD2
          8. 9.2.1.1.8  PPD Pin Divider Network, RPPD1, RPPD2
          9. 9.2.1.1.9  Setting Frequency (RFRS) and Synchronization
          10. 9.2.1.1.10 Bias Supply Requirements and CVCC
          11. 9.2.1.1.11 TPH, TPL, and BT Interface
          12. 9.2.1.1.12 Secondary Soft Start
          13. 9.2.1.1.13 Frequency Dithering for Conducted Emissions Control
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 EMI Containment
    4. 11.4 Thermal Considerations and OTSD
    5. 11.5 ESD
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.8 Line Undervoltage Protection and Converter Operation

When the input power source is removed, there are circumstances where stress may occur on the power components. For example with ACF topology, as VVDD-RTN gradually decreases the converter's operating duty cycle must compensate for the lower input voltage. At minimum input voltage the duty cycle nears its maximum value (DMAX), and the voltage across the clamp capacitor approaches its highest value since the transformer must be reset in a relatively short time. This results in potentially damaging overvoltage and oscillations. Also during next power up, due to precharged clamp capacitor, the soft-start could cause transformer saturation.

There are also situations where the output voltage capacitor may be able to back drive its secondary-side sync MOSFET(s) after the converter switching has stopped completely, either temporarily or not. Such situation could apply to both ACF and flyback (at power down or next soft-start) configurations.

To address this case, once the LINEUV voltage falls below VLIUVF, the TPS23730 transitions to soft-stop mode. It turns on temporarily the startup to maintain VVCC, then uses the SST control to ramp down the switching MOSFET peak current. As a result, the converter output is discharged in a controlled way, the energy of the output capacitor being sent back to the input bulk capacitor. Also note that at beginning of soft-stop, the TPS23730 temporarily forces the peak current to a low value (VCS maximum at approximately 50 mV), until SST voltage becomes low enough to decrease it further. This advanced feature allows the soft-stop to immediately start discharging the output capacitor, regardless of the output load level, minimizing any system tradeoffs for optimum switching MOSFETs protection. See Figure 8-13.

GUID-500EB189-E0C9-41CC-9AC2-85C1A94B2A3D-low.gifFigure 8-13 Soft-Stop Operation

Once the soft-stop operation has been completed and to avoid subsequent oscillations caused by the impact of the energy transfer on the LINEUV voltage, an internal load (~7 mA) is applied on VDD for approximately 160 ms, before the converter is allowed to restart.