SLVSER6B May   2020  – November 2020 TPS23730

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: DC-DC Controller Section
    6. 7.6 Electrical Characteristics PoE
    7.     14
    8. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CLSA, CLSB Classification
      2. 8.3.2  DEN Detection and Enable
      3. 8.3.3  APD Auxiliary Power Detect
      4. 8.3.4  PPD Power Detect
      5. 8.3.5  Internal Pass MOSFET
      6. 8.3.6  TPH, TPL and BT PSE Type Indicators
      7. 8.3.7  DC-DC Controller Features
        1. 8.3.7.1 VCC, VB, VBG and Advanced PWM Startup
        2.       28
        3. 8.3.7.2 CS, Current Slope Compensation and Blanking
        4. 8.3.7.3 COMP, FB, EA_DIS, CP, PSRS and Opto-less Feedback
        5. 8.3.7.4 FRS Frequency Setting and Synchronization
        6. 8.3.7.5 DTHR and Frequency Dithering for Spread Spectrum Applications
        7. 8.3.7.6 SST and Soft-Start of the Switcher
        8. 8.3.7.7 SST, I_STP, LINEUV and Soft-Stop of the Switcher
      8. 8.3.8  Switching FET Driver - GATE, GTA2, DT
      9. 8.3.9  EMPS and Automatic MPS
      10. 8.3.10 VDD Supply Voltage
      11. 8.3.11 RTN, AGND, GND
      12. 8.3.12 VSS
      13. 8.3.13 Exposed Thermal pads - PAD_G and PAD_S
    4. 8.4 Device Functional Modes
      1. 8.4.1  PoE Overview
      2. 8.4.2  Threshold Voltages
      3. 8.4.3  PoE Start-Up Sequence
      4. 8.4.4  Detection
      5. 8.4.5  Hardware Classification
      6. 8.4.6  Maintain Power Signature (MPS)
      7. 8.4.7  Advanced Start-Up and Converter Operation
      8. 8.4.8  Line Undervoltage Protection and Converter Operation
      9. 8.4.9  PD Self-Protection
      10. 8.4.10 Thermal Shutdown - DC-DC Controller
      11. 8.4.11 Adapter ORing
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1  Input Bridges and Schottky Diodes
          2. 9.2.1.1.2  Input TVS Protection
          3. 9.2.1.1.3  Input Bypass Capacitor
          4. 9.2.1.1.4  Detection Resistor, RDEN
          5. 9.2.1.1.5  Classification Resistor, RCLSA and RCLSB.
          6. 9.2.1.1.6  Dead Time Resistor, RDT
          7. 9.2.1.1.7  APD Pin Divider Network, RAPD1, RAPD2
          8. 9.2.1.1.8  PPD Pin Divider Network, RPPD1, RPPD2
          9. 9.2.1.1.9  Setting Frequency (RFRS) and Synchronization
          10. 9.2.1.1.10 Bias Supply Requirements and CVCC
          11. 9.2.1.1.11 TPH, TPL, and BT Interface
          12. 9.2.1.1.12 Secondary Soft Start
          13. 9.2.1.1.13 Frequency Dithering for Conducted Emissions Control
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 EMI Containment
    4. 11.4 Thermal Considerations and OTSD
    5. 11.5 ESD
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.6 TPH, TPL and BT PSE Type Indicators

The state of TPH and TPL is used to provide information relative to the allocated power. The encoding can be either parallel or serial (TPL only), selectable with SCDIS input. Table 8-2 lists the parallel encoding corresponding to various combinations of PSE Type, PD Class and allocated power. The allocated power is determined by the number of classification cycles having been received. The PSE may also allocate a lower power than what the PD is requesting, in which case there is power demotion. The BT output also indicates if a PSE applying an IEEE802.3bt (Type 3 or 4) mutual identification scheme has been identified.

Serial encoding can be selected by tying SCDIS to VSS. See Table 8-3 which lists the TPL serial encoding versus allocated power. In this case, TPH becomes high impedance.

Table 8-2 TPH, TPL and Allocated Power Truth Table, with APD and PPD Low, SCDIS Open
PSE TYPEPD CLASSNUMBER OF CLASS CYCLESPSE ALLOCATED POWER AT PD (W)TPH(2)TPL
1-40112.95HIGHHIGH
1-4113.84HIGHHIGH
1-4216.49HIGHHIGH
1-43112.95HIGHHIGH
24225.5HIGHLOW
3-442-325.5HIGHLOW
3-45440LOWHIGH
3-46451LOWHIGH
PoE++5,6--LOW(1)HIGH
(1) If PoE++ PSE, the BT output is also high.
(2) If APD or PPD is high, both TPH and TPL outputs become low.
Table 8-3 TPL Duty-Cycle and Allocated Power Truth Table, with APD and PPD Low, SCDIS Low
PSE TYPEPD CLASSNUMBER OF CLASS CYCLESPSE ALLOCATED POWER AT PD (W)TPL(1)
1-40112.95HIGH
1-4113.84HIGH
1-4216.49HIGH
1-43112.95HIGH
24225.5LOW
3-442-325.5LOW
3-45440LOW_25%
3-46451LOW_25%
PoE++5,6--LOW_50%
(1) If APD or PPD is high, TPL output becomes low with 75% duty-cycle.

During startup, the TPH, TPL and BT outputs are enabled only once the DC-DC controller has reached steady-state, the soft-start having been completed. These 3 outputs will return to a high-impedance state in any of the following cases:

  • DC-DC controller is back to soft-start mode
  • DC-DC controller transitions to soft-stop mode
  • DC-DC controller shuts off due to reasons including VVCC falling below VCUVLO_F, or the PoE hotswap is in inrush limit while APD is low
  • The device enters thermal shutdown

Note that in all these cases, as long as VDD-to-VSS voltage remains above the mark reset threshold, the internal logic state of these signals is remembered such that these outputs will be activated accordingly after the soft-start has completed. This circuit resets when the VDD-to-VSS voltage drops below the mark reset threshold. The TPH, TPL and BT pins can be left unconnected if not used.