Hardware classification allows a PSE to determine a PD’s power requirements before powering, and helps with power management once power is applied. Type 2, 3, and 4 hardware classification permits high power PDs to determine whether the PSE can support its high-power operation. The number of class cycles generated by the PSE prior to turn on indicates to the PD if it allots the power requested or if the allocated power is less than requested, in which case there is power demotion.

A Type 2 PD always presents Class 4 in hardware to indicate that it is a 25.5W device. A Class 5 or 6 Type 3 PD presents Class 4 in hardware during the first two class events and it presents Class 0 or 1, respectively, for all subsequent class events. A Class 7 or 8 Type 4 PD presents Class 4 in hardware during the first two class events and it presents Class 2 or 3, respectively, for all subsequent class events. A Type 1 PSE will treat a Class 4 to 8 device like a Class 0 device, allotting 13 W if it chooses to power the PD. A Type 2 PSE will treat a Class 5 to 8 device like a Class 4 device, allotting 25.5W if it chooses to power the PD. A Class 4 PD that receives a 2-event class, a Class 5 or 6 PD that receives a 4-event class, or a Class 7 or 8 PD that receives a 5-event class, understands that the PSE has agreed to allocate the PD requested power. In the case where there is power demotion, the PD may choose to not start, or to start while not drawing more power than initially allocated, and request more power through the DLL after startup. The standard requires a Type 2, 3 or 4 PD to indicate that it is underpowered if this occurs. Startup of a high-power PD at lower power than requested implicitly requires some form of powering down sections of the application circuits.

The maximum power entries in Table 8-1 determine the class the PD must advertise. The PSE may disconnect a PD if it draws more than its stated class power, which may be the hardware class or a DLL-derived power level. The standard permits the PD to draw limited current peaks that increase the instantaneous power above the Table 8-1 limit; however, the average power requirement always applies.

The TPS23730 implements one- to four-event classification. R_CLSA and R_CLSB resistor values define the class of the PD. DLL communication is implemented by the Ethernet communication system in the PD and is not implemented by the TPS23730.

The TPS23730 disables classification above V_{CU_OFF} to avoid excessive power dissipation. CLSA/B voltage is turned off during PD thermal limiting or when APD or DEN is active. The CLSA and CLSB outputs are inherently current-limited, but should not be shorted to V_SS for long periods of time.

Figure 8-8 shows how classification works for the TPS23730. Transition from state-to-state occurs when comparator thresholds are crossed (see Figure 8-5 and Figure 8-6). These comparators have hysteresis, which adds inherent memory to the machine. Operation begins at idle (unpowered by PSE) and proceeds with increasing voltage from left to right. A 2- to 4-event classification follows the (heavy lined) path towards the bottom, ending up with a latched TPL/TPH decode along the lower branch that is highlighted. Once the valid path to the PSE detection is broken, the input voltage must transition below the mark reset threshold to start anew.

Figure 8-8 Up to Four-Event Class Internal States