SLVSER6B May   2020  – November 2020 TPS23730

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: DC-DC Controller Section
    6. 7.6 Electrical Characteristics PoE
    7.     14
    8. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CLSA, CLSB Classification
      2. 8.3.2  DEN Detection and Enable
      3. 8.3.3  APD Auxiliary Power Detect
      4. 8.3.4  PPD Power Detect
      5. 8.3.5  Internal Pass MOSFET
      6. 8.3.6  TPH, TPL and BT PSE Type Indicators
      7. 8.3.7  DC-DC Controller Features
        1. 8.3.7.1 VCC, VB, VBG and Advanced PWM Startup
        2.       28
        3. 8.3.7.2 CS, Current Slope Compensation and Blanking
        4. 8.3.7.3 COMP, FB, EA_DIS, CP, PSRS and Opto-less Feedback
        5. 8.3.7.4 FRS Frequency Setting and Synchronization
        6. 8.3.7.5 DTHR and Frequency Dithering for Spread Spectrum Applications
        7. 8.3.7.6 SST and Soft-Start of the Switcher
        8. 8.3.7.7 SST, I_STP, LINEUV and Soft-Stop of the Switcher
      8. 8.3.8  Switching FET Driver - GATE, GTA2, DT
      9. 8.3.9  EMPS and Automatic MPS
      10. 8.3.10 VDD Supply Voltage
      11. 8.3.11 RTN, AGND, GND
      12. 8.3.12 VSS
      13. 8.3.13 Exposed Thermal pads - PAD_G and PAD_S
    4. 8.4 Device Functional Modes
      1. 8.4.1  PoE Overview
      2. 8.4.2  Threshold Voltages
      3. 8.4.3  PoE Start-Up Sequence
      4. 8.4.4  Detection
      5. 8.4.5  Hardware Classification
      6. 8.4.6  Maintain Power Signature (MPS)
      7. 8.4.7  Advanced Start-Up and Converter Operation
      8. 8.4.8  Line Undervoltage Protection and Converter Operation
      9. 8.4.9  PD Self-Protection
      10. 8.4.10 Thermal Shutdown - DC-DC Controller
      11. 8.4.11 Adapter ORing
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1  Input Bridges and Schottky Diodes
          2. 9.2.1.1.2  Input TVS Protection
          3. 9.2.1.1.3  Input Bypass Capacitor
          4. 9.2.1.1.4  Detection Resistor, RDEN
          5. 9.2.1.1.5  Classification Resistor, RCLSA and RCLSB.
          6. 9.2.1.1.6  Dead Time Resistor, RDT
          7. 9.2.1.1.7  APD Pin Divider Network, RAPD1, RAPD2
          8. 9.2.1.1.8  PPD Pin Divider Network, RPPD1, RPPD2
          9. 9.2.1.1.9  Setting Frequency (RFRS) and Synchronization
          10. 9.2.1.1.10 Bias Supply Requirements and CVCC
          11. 9.2.1.1.11 TPH, TPL, and BT Interface
          12. 9.2.1.1.12 Secondary Soft Start
          13. 9.2.1.1.13 Frequency Dithering for Conducted Emissions Control
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 EMI Containment
    4. 11.4 Thermal Considerations and OTSD
    5. 11.5 ESD
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics: DC-DC Controller Section

Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLSA, CLSB, TPH, TPL, BT, SCDIS and PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV, DT and DTHR connected to VB; PPD connected to VSS; CVB = CVBG = 0.1 μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; 8.5 V ≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.
[VVSS = VRTN], all voltages referred to VRTN , VAGND and VGND unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC-DC SUPPLY (VCC)
VCUVLO_R Undervoltage lockout VVCC rising 8 8.25 8.5 V
VCUVLO_F VVCC falling, VFB = VRTN 5.85 6.1 6.35 V
VCUVLO_H Hysteresis(1) 2 2.15 2.3 V
IRUN Operating current VVCC = 10 V, VFB = VRTN , RDT = 24.9 kΩ, CP with 2-kΩ pull up to 30 V  1.2 2 2.4 mA
IVC_ST Startup source current VAPD = 2.5 V
VVDD ≥ 28 V, VVCC = 11.7 V 21.5 30 34 mA
VVDD = 10.2 V, VVCC = 8.6 V 1 6 17.5
VVDD = 10.2 V, VVCC = 6.8 V 8 16 32
tST Startup time, CVCC = 1 μF VVDD = 10.2 V, VVCC(0) = 0 V, measure time until VCUVLO_R 0.25 0.7 1.15 ms
VVDD = 35 V, VVCC(0) = 0 V, measure time until VCUVLO_R 0.24 0.35 0.48 ms
VVC_ST VCC startup voltage Measure VVCC during startup, IVCC = 0 mA 11 12.5 14 V
Measure VVCC during startup, IVCC = 21.5 mA 11 12.5 14
VVC_SSTP VCC soft-stop voltage VLINEUV < VLIUVF, Measure VVCC during soft-stop, IVCC = 0 mA 11 12.5 14 V
VLINEUV < VLIUVF, Measure VVCC during soft-stop, IVCC = 21.5 mA 11 12.5 14
VB
Voltage VFB = VRTN, 8.5 V ≤ VVCC ≤ 16 V, 0 ≤ IVB ≤ 5 mA 4.75 5.0 5.25 V
DC-DC TIMING (FRS)
fSW Switching frequency VFB = VRTN, Measure at GATE 223 248 273 kHz
DMAX Duty cycle VFB = VRTN, RDT = 24.9 kΩ, Measure at GATE 74.5% 78.5% 82.5%
VSYNC Synchronization Input threshold 2 2.2 2.4 V
FREQUENCY DITHERING RAMP GENERATOR (DTHR)
IDTRCH Charging (sourcing) current 0.5 V < VDTHR < 1.5 V 3 x IFRS µA
47.2 49.6 52.1 µA
IDTRDC Discharging (sinking) current 0.5 V < VDTHR < 1.5 V 3 x IFRS µA
47.2 49.6 52.1 µA
VDTUT Dithering upper threshnold VDTHR rising until IDTHR > 0 1.41 1.513 1.60 V
VDTLT Dithering lower threshold VDTHR falling until IDTHR < 0 0.43 0.487 0.54 V
VDTPP Dithering pk-pk amplitude 1.005 1.026 1.046 V
ERROR AMPLIFIER (FB, COMP)
VREFC Feedback regulation voltage 1.723 1.75 1.777 V
IFB_LK FB leakage current (source or sink) VFB = 1.75 V 0.5 μA
GBW Small signal unity gain bandwidth 0.9 1.2 MHz
AOL Open loop voltage gain 70 80 db
VZDC 0% duty-cycle threshold VCOMP falling until GATE switching stops 1.35 1.5 1.65 V
ICOMPH COMP source current VFB = VRTN , VCOMP = 3 V 1 mA
ICOMPL COMP sink current VFB = VVB , VCOMP = 1.25 V 2.1 6 mA
VCOMPH COMP high voltage VFB = VRTN, 15 kΩ from COMP to RTN 4 VB V
VCOMPL COMP low voltage VFB = VVB, 15 kΩ from COMP to VB 1.1 V
COMP input resistance, error amplifier disabled EA_DIS open 70 100 130 kΩ
COMP to CS gain ΔVCS / ΔVCOMP , 0 V < VCS < 0.22 V 0.19 0.2 0.21 V/V
SOFT-START, SOFT-STOP (SST, I_STP)
ISSC Charge current SST charging, 6.35 V ≤ VVCC ≤ 16 V 7.5 10 12.5 µA
ISSD Discharge current SST discharging, 6.35 V ≤ VVCC ≤ 16 V 3 4 5 µA
VSFST Soft-start lower threshold 0.15 0.2 0.25 V
VSTUOF Startup turn off threshold VSST rising until VCC startup turns off 1.99 2.1 2.21 V
VSSOFS Soft-start offset voltage, closed-loop mode VFB = VRTN, VSST rising until start of switching 0.2 0.25 0.3 V
Soft-start offset voltage, peak current mode VCOMP = VVB, VSST rising until start of switching, EA_DIS open 0.55 0.6 0.65 V
VSSCL Soft-start clamp 2.3 2.6 V
ISSD_SP SST discharge current in soft-stop mode RI_STP = 499 kΩ, VLINEUV < VLIUVF 1.5 2 2.5 µA
RI_STP = 16.5 kΩ, , VLINEUV < VLIUVF 52.5 60.6 67.5
VSSTPEND End of soft-stop threshold VFB = VRTN, VLINEUV < VLIUVF 0.15 0.2 0.25 V
CURRENT SENSE (CS)
VCSMAX Maximum threshold voltage VFB = VRTN, VCS rising 0.227 0.25 0.273 V
tOFFD_IL Current limit turn off delay VCS = 0.3 V 25 41 60 ns
tOFFD_PW PWM comparator turn off delay VCS = 0.15 V, EA_DIS open, VCOMP = 2 V 25 41 60 ns
Blanking delay In addtition to tOFFD_IL and tOFFD_PW 75 95 115 ns
VSLOPE Internal slope compensation voltage VFB = VRTN, Peak voltage at maximum duty cycle, referred to CS 51 66 79 mV
ISL_EX Peak slope compensation current VFB = VRTN, ICS at maximum duty cycle (ac component) 14 20 26 μA
Bias current DC component of CS current -3 -2 -1 μA
LINE UNDERVOLTAGE, SOFT-STOP (LINEUV)
VLIUVF LINEUV falling threshold voltage VLINEUV falling 2.86 2.918 2.976 V
VLIUVH Hysteresis(1) 57 82 107 mV
Leakage current VLINEUV = 3 V 1 µA
DEAD TIME (DT)
tDT1 Dead time RDT = 24.9 kΩ, GAT2 ↑ to GATE ↑ VFB = VRTN , VPSRS = 0 V, EA_DIS open, VCOMP = VVB , CGATE = 1 nF, CGAT2 = 0.5 nF,
VVCC = 10 V		 40 50 62.5 ns
tDT2 RDT = 24.9 kΩ, GATE ↓ to GAT2 ↓ 40 50 62.5
tDT1 RDT = 75 kΩ, GAT2 ↑ to GATE ↑ 120 150 188
tDT2 RDT = 75 kΩ, GATE ↓ to GAT2 ↓ 120 150 188
GATE
Peak source current VFB = VRTN, VVCC = 10 V, VGATE = 0 V, pulsed measurement 0.3 0.5 0.8 A
Peak sink current VFB = VRTN, VVCC = 10 V, VGATE = 10 V, pulsed measurement 0.6 0.9 1.45 A
Rise time(2) tprr10-90, CGATE = 1 nF, VVCC = 10 V 30 ns
Fall time(2) tpff90-10, CGATE = 1 nF, VVCC = 10 V 15 ns
GAT2
Peak source current VFB = VRTN , VVCC = 10 V, RDT = 24.9 kΩ, VGAT2 = 0 V, pulsed measurement 0.3 0.5 0.8 A
Peak sink current VFB = VRTN , VVCC = 10 V, RDT = 24.9 kΩ, VGAT2 = 10 V, pulsed measurement 0.3 0.45 0.72 A
Rise time(2) tprr10-90 , CGAT2 = 0.5 nF , VVCC = 10 V 15 ns
Fall time(2) tpff90-10 , CGAT2 = 0.5 nF , VVCC = 10 V 15 ns
CLAMPING FET (CP)
RDS(ON)CL CP FET on resistance ICP = 100 mA 1.5 3.3 Ω
CLAMPING DIODE (CP)
VFCP CP Diode forward voltage VPSRS = 0 V, ICP = 15 mA 0.45 0.6 0.85 V
CP Leakage current VPSRS = 0 V, VCP = 45 V 20 µA
AUXILIARY POWER DETECTION (APD)
VAPDEN APD threshold voltage VAPD rising 1.42 1.5 1.58 V
VAPDH Hysteresis(1) 0.075 0.095 0.115 V
Leakage current VAPD = 5 V 1 µA
PPD
VPPDEN PPD threshold voltage VVDD > 16 V, VPPD - VVSS rising, PD input UVLO disable 2.34 2.5 2.66 V
VPPDH Hysteresis(1) 0.47 0.5 0.53
IPPD PPD sink current VPPD - VVSS = 3 V 2.5 5 7.5 µA
THERMAL SHUTDOWN
Turnoff temperature 145 155 165 °C
Hysteresis(2) 15 °C
(1) The hysteresis tolerance tracks the rising threshold for a given device.
(2) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.