SLVSER8A June   2020  – September 2020 TPS23734

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: DC-DC Controller Section
    6. 7.6 Electrical Characteristics PoE
    7.     15
    8. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CLS Classification
      2. 8.3.2  DEN Detection and Enable
      3. 8.3.3  APD Auxiliary Power Detect
      4. 8.3.4  Internal Pass MOSFET
      5. 8.3.5  T2P and APDO Indicators
      6. 8.3.6  DC-DC Controller Features
        1. 8.3.6.1 VCC, VB, VBG and Advanced PWM Startup
        2.       28
        3. 8.3.6.2 CS, Current Slope Compensation and blanking
        4. 8.3.6.3 COMP, FB, EA_DIS, CP, PSRS and Opto-less Feedback
        5. 8.3.6.4 FRS Frequency Setting and Synchronization
        6. 8.3.6.5 DTHR and Frequency Dithering for Spread Spectrum Applications
        7. 8.3.6.6 SST and Soft-Start of the Switcher
        8. 8.3.6.7 SST, I_STP, LINEUV and Soft-Stop of the Switcher
      7. 8.3.7  Switching FET Driver - GATE, GTA2, DT
      8. 8.3.8  EMPS and Automatic MPS
      9. 8.3.9  VDD Supply Voltage
      10. 8.3.10 RTN, AGND, GND
      11. 8.3.11 VSS
      12. 8.3.12 Exposed Thermal pads - PAD_G and PAD_S
    4. 8.4 Device Functional Modes
      1. 8.4.1  PoE Overview
      2. 8.4.2  Threshold Voltages
      3. 8.4.3  PoE Start-Up Sequence
      4. 8.4.4  Detection
      5. 8.4.5  Hardware Classification
      6. 8.4.6  Maintain Power Signature (MPS)
      7. 8.4.7  Advanced Start-Up and Converter Operation
      8. 8.4.8  Line Undervoltage Protection and Converter Operation
      9. 8.4.9  PD Self-Protection
      10. 8.4.10 Thermal Shutdown - DC-DC Controller
      11. 8.4.11 Adapter ORing
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1  Input Bridges and Schottky Diodes
          2. 9.2.1.1.2  Input TVS Protection
          3. 9.2.1.1.3  Input Bypass Capacitor
          4. 9.2.1.1.4  Detection Resistor, RDEN
          5. 9.2.1.1.5  Classification Resistor, RCLS.
          6. 9.2.1.1.6  Dead Time Resistor, RDT
          7. 9.2.1.1.7  APD Pin Divider Network, RAPD1, RAPD2
          8. 9.2.1.1.8  Setting Frequency (RFRS) and Synchronization
          9. 9.2.1.1.9  Bias Supply Requirements and CVCC
          10. 9.2.1.1.10 APDO, T2P Interface
          11. 9.2.1.1.11 Secondary Soft Start
          12. 9.2.1.1.12 Frequency Dithering for Conducted Emissions Control
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 EMI Containment
    4. 11.4 Thermal Considerations and OTSD
    5. 11.5 ESD
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Electrical Characteristics PoE

Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLS, T2P, APDO, and PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV, DT and DTHR connected to VB; CVB = CVBG = 0.1 μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.
VVCC-RTN = 0 V, all voltages referred to VVSS unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD DETECTION (DEN)
Detection bias current DEN open, VVDD = 10 V, Not in mark, Measure IVDD + IRTN 3.5 6.9 13.9 µA
Ilkg DEN leakage current VDEN = VVDD = 60 V, Float RTN, Measure IDEN 0.1 5 µA
Detection current Measure IVDD + IDEN + IRTN, VVDD = 1.4 V 53.5 56.5 58.6 μA
Measure IVDD + IDEN + IRTN, VVDD = 10 V, Not in mark 391 398 406.2 μA
VPD_DIS Hotswap disable threshold DEN falling 3 4 5 V
PD CLASSIFICATION (CLS)
ICLS Classification signature current RCLS = 806 Ω 13 V ≤ VDD ≤ 21 V, Measure IVDD + IDEN + IRTN 1.9 2.5 2.9 mA
RCLS = 130 Ω 13 V ≤ VDD ≤ 21 V, Measure IVDD + IDEN + IRTN 9.9 10.6 11.3 mA
RCLS = 69.8 Ω 13 V ≤ VDD ≤ 21 V, Measure IVDD + IDEN + IRTN 17.6 18.6 19.4 mA
RCLS = 46.4 Ω 13 V ≤ VDD ≤ 21 V, Measure IVDD + IDEN + IRTN 26.5 27.9 29.3 mA
RCLS = 32 Ω 13 V ≤ VDD ≤ 21 V, Measure IVDD + IDEN + IRTN 37.8 39.9 42 mA
ICLS Classification signature current, 3rd class event  RCLS  = 32 Ω 13 V ≤ VDD ≤ 21 V, Measure IVDD + IDEN + IRTN 37.8 39.9 42 mA
VCL_ON Classification regulator lower threshold rising VVDD rising, ICLS ↑ 11.4 12.2 13 V
VCL_H Classification regulator lower threshold Hysteresis(1) 0.8 1.2 1.6 V
VCU_OFF Classification regulator upper threshold VVDD rising, ICLS ↓ 21 22 23 V
VCU_H Hysteresis(1) 0.5 0.77 1 V
VMSR Mark state reset threshold VVDD falling 3 3.9 5 V
Mark state resistance 2-point measurement at 5 V and 10.1 V 6 10 12 kΩ
Ilkg Leakage current VVDD = 60 V, VCLS = 0 V, VDEN = VVSS, Measure ICLS 1 μA
tLCF_PD Long first class event timing Class 1st event time duration for short MPS 76 81.5 87 ms
RTN (PASS DEVICE)
ON-resistance 0.3 0.55 Ω
ILIM Current limit VRTN = 1.5 V, pulsed measurement 0.75 0.925 1.1 A
IIRSH inrush current limit VRTN = 2 V, VVDD: 20 V → 48 V, measure IRTN , pulsed measurement 100 140 180 mA
Inrush termination Percentage of inrush current. 80% 90% 99%
tINR_DEL Inrush delay 80 84 88 ms
Foldback voltage threshold VRTN rising 13.5 14.8 16.1 V
Foldback deglitch time VRTN rising to when current limit changes to inrush current limit. This applies in normal operating condition or during auto MPS mode. 1.5 1.8 2.1 ms
Leakage current VVDD = VRTN = 100 V, VDEN = VVSS 70 μA
PSE TYPE INDICATION (T2P)
Output low voltage IT2P = 1 mA, after 2- or 3-event classification, startup has completed, VRTN = 0 V 0.27 0.5 V
Leakage current VT2P-RTN = 10 V, VRTN = 0 V 1 µA
PD INPUT SUPPLY (VDD)
VUVLO_R Undervoltage lockout threshold VVDD rising 35.8 37.6 39.5 V
VUVLO_F Undervoltage lockout threshold VVDD falling 30.5 32 33.6 V
VUVLO_H Undervoltage lockout threshold Hysteresis (1) 5.7 6.0 6.3 V
IVDD_ON Operating current 40 V ≤ VVDD ≤ 60 V, Startup completed, VVCC = 10 V, Measure IVDD 650 1040 µA
IVDD_OFF Off-state current RTN, GND and VCC open, VVDD = 30 V, Measure IVDD 730 µA
MPS
IMPSL MPS total VSS current for Type 1-2 PSE EMPS open, inrush delay has completed, 0 mA ≤ IRTN ≤ 10 mA, measure IVSS 10 12.5 15.5 mA
IMPSH MPS total VSS current for Type 3-4 PSE EMPS open, inrush delay has completed, 0 mA ≤ IRTN ≤ 16 mA, measure IVSS 16.25 19 21.5 mA
MPS pulsed mode duty cycle for Type 1-2 PSE MPS pulsed current duty-cycle EMPS open 26.2% 26.6% 26.9%
tMPSL MPS pulsed current ON time EMPS open 76 81.5 87 ms
MPS pulsed current OFF time EMPS open 225 245 ms
MPS pulsed mode duty-cycle for Type 3-4 PSE MPS pulsed current duty-cycle, no pulse stretching EMPS open 2.9% 3.0% 3.1%
tMPSH MPS pulsed current ON time, no pulse stretching EMPS open 7.2 7.7 8.1 ms
MPS pulsed current OFF time EMPS open 238 250 265 ms
MPS pulsed current ON time stretching limit EMPS open 54 57 62 ms
THERMAL SHUTDOWN
Turnoff temperature 148 158 168 °C
Hysteresis(2) 15 °C
(1) The hysteresis tolerance tracks the rising threshold for a given device.
(2) These parameters are provided for reference only.