SLVS933D July   2009  – December 2020 TPS23753A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Product Information
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Controller Section Only
    6. 7.6 Electrical Characteristics: PoE and Control
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Description
        1. 8.3.1.1  APD
        2. 8.3.1.2  BLNK
        3. 8.3.1.3  CLS
        4. 8.3.1.4  CS
        5. 8.3.1.5  CTL
        6. 8.3.1.6  DEN
        7. 8.3.1.7  FRS
        8. 8.3.1.8  GATE
        9. 8.3.1.9  RTN
        10. 8.3.1.10 VB
        11. 8.3.1.11 VC
        12. 8.3.1.12 VDD
        13. 8.3.1.13 VDD1
        14. 8.3.1.14 VSS
    4. 8.4 Device Functional Modes
      1. 8.4.1  Threshold Voltages
      2. 8.4.2  PoE Start-Up Sequence
      3. 8.4.3  Detection
      4. 8.4.4  Hardware Classification
      5. 8.4.5  Maintain Power Signature (MPS)
      6. 8.4.6  TPS23753A Operation
        1. 8.4.6.1 Start-Up and Converter Operation
        2. 8.4.6.2 PD Self-Protection
        3. 8.4.6.3 Converter Controller Features
      7. 8.4.7  Special Switching MOSFET Considerations
      8. 8.4.8  Thermal Considerations
      9. 8.4.9  FRS and Synchronization
      10. 8.4.10 Blanking – RBLNK
      11. 8.4.11 Current Slope Compensation
      12. 8.4.12 Adapter ORing
      13. 8.4.13 Protection
      14. 8.4.14 Frequency Dithering for Conducted Emissions Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.6.1 Start-Up and Converter Operation

The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits discharges CIN, CVC, and CVB while the PD is unpowered. Thus VRTN-VDD will be a small voltage just after full voltage is applied to the PD, as seen in Figure 8-3.

The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When VDD rises above the UVLO turnon threshold (VUVLO-R, approximately 35 V) with RTN high, the TPS23753A enables the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of Figure 8-4 for an example. Converter switching is disabled while CIN charges and VRTN falls from VDD to nearly VSS; however, the converter start-up circuit is allowed to charge CVC. Once the inrush current falls about 10% below the inrush current limit, the PD control switches to the operational level (approximately 450 mA) and converter switching is permitted.

Converter switching is allowed if the PD is not in inrush and the VC UVLO circuit permits it. Continuing the start-up sequence shown in Figure 8-4, VVC rises as the start-up current source charges CVC and M1 switching is inhibited by the status of the VC UVLO. The VB regulator powers the internal converter circuits as VVC rises. Start-up current is turned off, converter switching is enabled, and a soft-start cycle starts when VVC exceeds UVLO1 (approximately 9 V). VVC falls as it powers both the internal circuits and the switching MOSFET gate. If the converter control-bias output rises to support VVC before it falls to UVLO1 – UVLO1H (approximately 5.5 V), a successful start-up occurs. Figure 8-4 shows a small droop in VVC while the output voltage rises smoothly and a successful start-up occurs.

GUID-812EA6B0-F596-47A9-AABE-CC1DB6A74634-low.gifFigure 8-4 Power Up and Start

If VVDD-VSS drops below the lower PoE UVLO (UVLOR – UVLOH, approximately 30.5 V), the hotswap MOSFET is turned off, but the converter still runs. The converter stops if VVC falls below the converter UVLO (UVLO1 – UVLOH, approximately 5.5 V), the hotswap is in inrush current limit, or 0% duty cycle is demanded by VCTL (VCTL < VZDC, approximately 1.5 V), or the converter is in thermal shutdown.